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409 lines
12 KiB
409 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* arch/arm/probes/decode.h |
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* |
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* Copyright (C) 2011 Jon Medhurst <[email protected]>. |
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* |
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* Some contents moved here from arch/arm/include/asm/kprobes.h which is |
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* Copyright (C) 2006, 2007 Motorola Inc. |
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*/ |
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#ifndef _ARM_KERNEL_PROBES_H |
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#define _ARM_KERNEL_PROBES_H |
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#include <linux/types.h> |
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#include <linux/stddef.h> |
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#include <asm/probes.h> |
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#include <asm/kprobes.h> |
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void __init arm_probes_decode_init(void); |
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extern probes_check_cc * const probes_condition_checks[16]; |
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#if __LINUX_ARM_ARCH__ >= 7 |
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/* str_pc_offset is architecturally defined from ARMv7 onwards */ |
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#define str_pc_offset 8 |
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#define find_str_pc_offset() |
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#else /* __LINUX_ARM_ARCH__ < 7 */ |
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/* We need a run-time check to determine str_pc_offset */ |
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extern int str_pc_offset; |
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void __init find_str_pc_offset(void); |
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#endif |
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/* |
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* Update ITSTATE after normal execution of an IT block instruction. |
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* |
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* The 8 IT state bits are split into two parts in CPSR: |
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* ITSTATE<1:0> are in CPSR<26:25> |
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* ITSTATE<7:2> are in CPSR<15:10> |
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*/ |
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static inline unsigned long it_advance(unsigned long cpsr) |
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{ |
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if ((cpsr & 0x06000400) == 0) { |
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/* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */ |
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cpsr &= ~PSR_IT_MASK; |
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} else { |
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/* We need to shift left ITSTATE<4:0> */ |
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const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */ |
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unsigned long it = cpsr & mask; |
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it <<= 1; |
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it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */ |
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it &= mask; |
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cpsr &= ~mask; |
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cpsr |= it; |
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} |
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return cpsr; |
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} |
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static inline void __kprobes bx_write_pc(long pcv, struct pt_regs *regs) |
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{ |
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long cpsr = regs->ARM_cpsr; |
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if (pcv & 0x1) { |
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cpsr |= PSR_T_BIT; |
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pcv &= ~0x1; |
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} else { |
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cpsr &= ~PSR_T_BIT; |
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pcv &= ~0x2; /* Avoid UNPREDICTABLE address allignment */ |
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} |
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regs->ARM_cpsr = cpsr; |
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regs->ARM_pc = pcv; |
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} |
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#if __LINUX_ARM_ARCH__ >= 6 |
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/* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */ |
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#define load_write_pc_interworks true |
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#define test_load_write_pc_interworking() |
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#else /* __LINUX_ARM_ARCH__ < 6 */ |
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/* We need run-time testing to determine if load_write_pc() should interwork. */ |
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extern bool load_write_pc_interworks; |
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void __init test_load_write_pc_interworking(void); |
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#endif |
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static inline void __kprobes load_write_pc(long pcv, struct pt_regs *regs) |
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{ |
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if (load_write_pc_interworks) |
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bx_write_pc(pcv, regs); |
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else |
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regs->ARM_pc = pcv; |
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} |
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#if __LINUX_ARM_ARCH__ >= 7 |
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#define alu_write_pc_interworks true |
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#define test_alu_write_pc_interworking() |
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#elif __LINUX_ARM_ARCH__ <= 5 |
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/* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */ |
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#define alu_write_pc_interworks false |
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#define test_alu_write_pc_interworking() |
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#else /* __LINUX_ARM_ARCH__ == 6 */ |
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/* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */ |
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extern bool alu_write_pc_interworks; |
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void __init test_alu_write_pc_interworking(void); |
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#endif /* __LINUX_ARM_ARCH__ == 6 */ |
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static inline void __kprobes alu_write_pc(long pcv, struct pt_regs *regs) |
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{ |
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if (alu_write_pc_interworks) |
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bx_write_pc(pcv, regs); |
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else |
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regs->ARM_pc = pcv; |
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} |
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/* |
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* Test if load/store instructions writeback the address register. |
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* if P (bit 24) == 0 or W (bit 21) == 1 |
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*/ |
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#define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000) |
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/* |
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* The following definitions and macros are used to build instruction |
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* decoding tables for use by probes_decode_insn. |
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* |
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* These tables are a concatenation of entries each of which consist of one of |
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* the decode_* structs. All of the fields in every type of decode structure |
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* are of the union type decode_item, therefore the entire decode table can be |
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* viewed as an array of these and declared like: |
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* |
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* static const union decode_item table_name[] = {}; |
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* |
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* In order to construct each entry in the table, macros are used to |
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* initialise a number of sequential decode_item values in a layout which |
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* matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct |
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* decode_simulate by initialising four decode_item objects like this... |
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* |
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* {.bits = _type}, |
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* {.bits = _mask}, |
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* {.bits = _value}, |
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* {.action = _handler}, |
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* |
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* Initialising a specified member of the union means that the compiler |
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* will produce a warning if the argument is of an incorrect type. |
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* |
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* Below is a list of each of the macros used to initialise entries and a |
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* description of the action performed when that entry is matched to an |
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* instruction. A match is found when (instruction & mask) == value. |
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* |
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* DECODE_TABLE(mask, value, table) |
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* Instruction decoding jumps to parsing the new sub-table 'table'. |
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* |
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* DECODE_CUSTOM(mask, value, decoder) |
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* The value of 'decoder' is used as an index into the array of |
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* action functions, and the retrieved decoder function is invoked |
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* to complete decoding of the instruction. |
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* |
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* DECODE_SIMULATE(mask, value, handler) |
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* The probes instruction handler is set to the value found by |
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* indexing into the action array using the value of 'handler'. This |
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* will be used to simulate the instruction when the probe is hit. |
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* Decoding returns with INSN_GOOD_NO_SLOT. |
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* |
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* DECODE_EMULATE(mask, value, handler) |
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* The probes instruction handler is set to the value found by |
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* indexing into the action array using the value of 'handler'. This |
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* will be used to emulate the instruction when the probe is hit. The |
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* modified instruction (see below) is placed in the probes instruction |
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* slot so it may be called by the emulation code. Decoding returns |
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* with INSN_GOOD. |
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* |
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* DECODE_REJECT(mask, value) |
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* Instruction decoding fails with INSN_REJECTED |
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* |
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* DECODE_OR(mask, value) |
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* This allows the mask/value test of multiple table entries to be |
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* logically ORed. Once an 'or' entry is matched the decoding action to |
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* be performed is that of the next entry which isn't an 'or'. E.g. |
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* |
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* DECODE_OR (mask1, value1) |
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* DECODE_OR (mask2, value2) |
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* DECODE_SIMULATE (mask3, value3, simulation_handler) |
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* |
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* This means that if any of the three mask/value pairs match the |
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* instruction being decoded, then 'simulation_handler' will be used |
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* for it. |
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* |
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* Both the SIMULATE and EMULATE macros have a second form which take an |
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* additional 'regs' argument. |
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* |
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* DECODE_SIMULATEX(mask, value, handler, regs) |
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* DECODE_EMULATEX (mask, value, handler, regs) |
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* |
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* These are used to specify what kind of CPU register is encoded in each of the |
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* least significant 5 nibbles of the instruction being decoded. The regs value |
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* is specified using the REGS macro, this takes any of the REG_TYPE_* values |
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* from enum decode_reg_type as arguments; only the '*' part of the name is |
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* given. E.g. |
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* |
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* REGS(0, ANY, NOPC, 0, ANY) |
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* |
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* This indicates an instruction is encoded like: |
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* |
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* bits 19..16 ignore |
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* bits 15..12 any register allowed here |
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* bits 11.. 8 any register except PC allowed here |
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* bits 7.. 4 ignore |
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* bits 3.. 0 any register allowed here |
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* |
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* This register specification is checked after a decode table entry is found to |
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* match an instruction (through the mask/value test). Any invalid register then |
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* found in the instruction will cause decoding to fail with INSN_REJECTED. In |
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* the above example this would happen if bits 11..8 of the instruction were |
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* 1111, indicating R15 or PC. |
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* |
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* As well as checking for legal combinations of registers, this data is also |
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* used to modify the registers encoded in the instructions so that an |
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* emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.) |
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* |
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* Here is a real example which matches ARM instructions of the form |
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* "AND <Rd>,<Rn>,<Rm>,<shift> <Rs>" |
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* |
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* DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG, |
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* REGS(ANY, ANY, NOPC, 0, ANY)), |
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* ^ ^ ^ ^ |
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* Rn Rd Rs Rm |
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* |
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* Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because |
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* Rs == R15 |
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* |
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* Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the |
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* instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into |
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* the kprobes instruction slot. This can then be called later by the handler |
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* function emulate_rd12rn16rm0rs8_rwflags (a pointer to which is retrieved from |
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* the indicated slot in the action array), in order to simulate the instruction. |
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*/ |
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enum decode_type { |
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DECODE_TYPE_END, |
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DECODE_TYPE_TABLE, |
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DECODE_TYPE_CUSTOM, |
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DECODE_TYPE_SIMULATE, |
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DECODE_TYPE_EMULATE, |
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DECODE_TYPE_OR, |
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DECODE_TYPE_REJECT, |
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NUM_DECODE_TYPES /* Must be last enum */ |
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}; |
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#define DECODE_TYPE_BITS 4 |
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#define DECODE_TYPE_MASK ((1 << DECODE_TYPE_BITS) - 1) |
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enum decode_reg_type { |
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REG_TYPE_NONE = 0, /* Not a register, ignore */ |
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REG_TYPE_ANY, /* Any register allowed */ |
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REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */ |
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REG_TYPE_SP, /* Register must be SP */ |
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REG_TYPE_PC, /* Register must be PC */ |
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REG_TYPE_NOSP, /* Register must not be SP */ |
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REG_TYPE_NOSPPC, /* Register must not be SP or PC */ |
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REG_TYPE_NOPC, /* Register must not be PC */ |
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REG_TYPE_NOPCWB, /* No PC if load/store write-back flag also set */ |
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/* The following types are used when the encoding for PC indicates |
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* another instruction form. This distiction only matters for test |
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* case coverage checks. |
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*/ |
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REG_TYPE_NOPCX, /* Register must not be PC */ |
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REG_TYPE_NOSPPCX, /* Register must not be SP or PC */ |
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/* Alias to allow '0' arg to be used in REGS macro. */ |
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REG_TYPE_0 = REG_TYPE_NONE |
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}; |
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#define REGS(r16, r12, r8, r4, r0) \ |
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(((REG_TYPE_##r16) << 16) + \ |
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((REG_TYPE_##r12) << 12) + \ |
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((REG_TYPE_##r8) << 8) + \ |
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((REG_TYPE_##r4) << 4) + \ |
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(REG_TYPE_##r0)) |
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union decode_item { |
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u32 bits; |
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const union decode_item *table; |
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int action; |
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}; |
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struct decode_header; |
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typedef enum probes_insn (probes_custom_decode_t)(probes_opcode_t, |
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struct arch_probes_insn *, |
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const struct decode_header *); |
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union decode_action { |
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probes_insn_handler_t *handler; |
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probes_custom_decode_t *decoder; |
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}; |
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typedef enum probes_insn (probes_check_t)(probes_opcode_t, |
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struct arch_probes_insn *, |
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const struct decode_header *); |
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struct decode_checker { |
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probes_check_t *checker; |
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}; |
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#define DECODE_END \ |
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{.bits = DECODE_TYPE_END} |
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struct decode_header { |
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union decode_item type_regs; |
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union decode_item mask; |
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union decode_item value; |
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}; |
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#define DECODE_HEADER(_type, _mask, _value, _regs) \ |
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{.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)}, \ |
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{.bits = (_mask)}, \ |
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{.bits = (_value)} |
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struct decode_table { |
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struct decode_header header; |
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union decode_item table; |
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}; |
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#define DECODE_TABLE(_mask, _value, _table) \ |
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DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0), \ |
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{.table = (_table)} |
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struct decode_custom { |
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struct decode_header header; |
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union decode_item decoder; |
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}; |
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#define DECODE_CUSTOM(_mask, _value, _decoder) \ |
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DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0), \ |
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{.action = (_decoder)} |
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struct decode_simulate { |
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struct decode_header header; |
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union decode_item handler; |
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}; |
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#define DECODE_SIMULATEX(_mask, _value, _handler, _regs) \ |
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DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs), \ |
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{.action = (_handler)} |
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#define DECODE_SIMULATE(_mask, _value, _handler) \ |
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DECODE_SIMULATEX(_mask, _value, _handler, 0) |
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struct decode_emulate { |
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struct decode_header header; |
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union decode_item handler; |
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}; |
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#define DECODE_EMULATEX(_mask, _value, _handler, _regs) \ |
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DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs), \ |
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{.action = (_handler)} |
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#define DECODE_EMULATE(_mask, _value, _handler) \ |
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DECODE_EMULATEX(_mask, _value, _handler, 0) |
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struct decode_or { |
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struct decode_header header; |
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}; |
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#define DECODE_OR(_mask, _value) \ |
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DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0) |
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enum probes_insn { |
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INSN_REJECTED, |
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INSN_GOOD, |
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INSN_GOOD_NO_SLOT |
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}; |
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struct decode_reject { |
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struct decode_header header; |
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}; |
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#define DECODE_REJECT(_mask, _value) \ |
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DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0) |
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probes_insn_handler_t probes_simulate_nop; |
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probes_insn_handler_t probes_emulate_none; |
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int __kprobes |
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probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi, |
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const union decode_item *table, bool thumb, bool emulate, |
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const union decode_action *actions, |
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const struct decode_checker **checkers); |
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#endif
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