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415 lines
10 KiB
415 lines
10 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S |
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* |
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* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com) |
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* |
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* (Many of cache codes are from proc-arm926.S) |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/init.h> |
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#include <linux/pgtable.h> |
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#include <asm/assembler.h> |
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#include <asm/hwcap.h> |
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#include <asm/pgtable-hwdef.h> |
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#include <asm/ptrace.h> |
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#include "proc-macros.S" |
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/* |
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* ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache, |
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* comprising 256 lines of 32 bytes (8 words). |
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*/ |
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#define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */ |
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#define CACHE_DLINESIZE 32 /* fixed */ |
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#define CACHE_DSEGMENTS 4 /* fixed */ |
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#define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE) |
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#define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */ |
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.text |
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/* |
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* cpu_arm946_proc_init() |
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* cpu_arm946_switch_mm() |
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* |
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* These are not required. |
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*/ |
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ENTRY(cpu_arm946_proc_init) |
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ENTRY(cpu_arm946_switch_mm) |
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ret lr |
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/* |
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* cpu_arm946_proc_fin() |
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*/ |
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ENTRY(cpu_arm946_proc_fin) |
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
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bic r0, r0, #0x00001000 @ i-cache |
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bic r0, r0, #0x00000004 @ d-cache |
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mcr p15, 0, r0, c1, c0, 0 @ disable caches |
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ret lr |
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/* |
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* cpu_arm946_reset(loc) |
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* Params : r0 = address to jump to |
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* Notes : This sets up everything for a reset |
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*/ |
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.pushsection .idmap.text, "ax" |
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ENTRY(cpu_arm946_reset) |
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mov ip, #0 |
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mcr p15, 0, ip, c7, c5, 0 @ flush I cache |
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache |
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mcr p15, 0, ip, c7, c10, 4 @ drain WB |
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
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bic ip, ip, #0x00000005 @ .............c.p |
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bic ip, ip, #0x00001000 @ i-cache |
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
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ret r0 |
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ENDPROC(cpu_arm946_reset) |
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.popsection |
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/* |
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* cpu_arm946_do_idle() |
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*/ |
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.align 5 |
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ENTRY(cpu_arm946_do_idle) |
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt |
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ret lr |
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/* |
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* flush_icache_all() |
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* |
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* Unconditionally clean and invalidate the entire icache. |
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*/ |
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ENTRY(arm946_flush_icache_all) |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache |
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ret lr |
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ENDPROC(arm946_flush_icache_all) |
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/* |
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* flush_user_cache_all() |
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*/ |
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ENTRY(arm946_flush_user_cache_all) |
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/* FALLTHROUGH */ |
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/* |
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* flush_kern_cache_all() |
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* |
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* Clean and invalidate the entire cache. |
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*/ |
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ENTRY(arm946_flush_kern_cache_all) |
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mov r2, #VM_EXEC |
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mov ip, #0 |
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__flush_whole_cache: |
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH |
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache |
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#else |
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mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments |
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries |
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2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index |
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subs r3, r3, #1 << 4 |
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bcs 2b @ entries n to 0 |
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subs r1, r1, #1 << 29 |
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bcs 1b @ segments 3 to 0 |
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#endif |
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tst r2, #VM_EXEC |
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mcrne p15, 0, ip, c7, c5, 0 @ flush I cache |
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB |
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ret lr |
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/* |
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* flush_user_cache_range(start, end, flags) |
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* |
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* Clean and invalidate a range of cache entries in the |
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* specified address range. |
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* |
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* - start - start address (inclusive) |
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* - end - end address (exclusive) |
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* - flags - vm_flags describing address space |
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* (same as arm926) |
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*/ |
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ENTRY(arm946_flush_user_cache_range) |
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mov ip, #0 |
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sub r3, r1, r0 @ calculate total size |
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cmp r3, #CACHE_DLIMIT |
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bhs __flush_whole_cache |
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1: tst r2, #VM_EXEC |
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH |
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
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add r0, r0, #CACHE_DLINESIZE |
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
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add r0, r0, #CACHE_DLINESIZE |
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#else |
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry |
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
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add r0, r0, #CACHE_DLINESIZE |
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry |
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
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add r0, r0, #CACHE_DLINESIZE |
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#endif |
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cmp r0, r1 |
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blo 1b |
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tst r2, #VM_EXEC |
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB |
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ret lr |
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/* |
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* coherent_kern_range(start, end) |
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* |
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* Ensure coherency between the Icache and the Dcache in the |
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* region described by start, end. If you have non-snooping |
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* Harvard caches, you need to implement this function. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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*/ |
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ENTRY(arm946_coherent_kern_range) |
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/* FALLTHROUGH */ |
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/* |
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* coherent_user_range(start, end) |
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* |
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* Ensure coherency between the Icache and the Dcache in the |
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* region described by start, end. If you have non-snooping |
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* Harvard caches, you need to implement this function. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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* (same as arm926) |
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*/ |
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ENTRY(arm946_coherent_user_range) |
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bic r0, r0, #CACHE_DLINESIZE - 1 |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry |
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add r0, r0, #CACHE_DLINESIZE |
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cmp r0, r1 |
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blo 1b |
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mcr p15, 0, r0, c7, c10, 4 @ drain WB |
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mov r0, #0 |
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ret lr |
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/* |
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* flush_kern_dcache_area(void *addr, size_t size) |
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* |
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* Ensure no D cache aliasing occurs, either with itself or |
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* the I cache |
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* |
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* - addr - kernel address |
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* - size - region size |
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* (same as arm926) |
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*/ |
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ENTRY(arm946_flush_kern_dcache_area) |
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add r1, r0, r1 |
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
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add r0, r0, #CACHE_DLINESIZE |
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cmp r0, r1 |
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blo 1b |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache |
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mcr p15, 0, r0, c7, c10, 4 @ drain WB |
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ret lr |
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/* |
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* dma_inv_range(start, end) |
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* |
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* Invalidate (discard) the specified virtual address range. |
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* May not write back any entries. If 'start' or 'end' |
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* are not cache line aligned, those lines must be written |
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* back. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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* (same as arm926) |
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*/ |
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arm946_dma_inv_range: |
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
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tst r0, #CACHE_DLINESIZE - 1 |
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
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tst r1, #CACHE_DLINESIZE - 1 |
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry |
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#endif |
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bic r0, r0, #CACHE_DLINESIZE - 1 |
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
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add r0, r0, #CACHE_DLINESIZE |
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cmp r0, r1 |
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blo 1b |
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mcr p15, 0, r0, c7, c10, 4 @ drain WB |
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ret lr |
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/* |
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* dma_clean_range(start, end) |
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* |
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* Clean the specified virtual address range. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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* |
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* (same as arm926) |
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*/ |
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arm946_dma_clean_range: |
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
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bic r0, r0, #CACHE_DLINESIZE - 1 |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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add r0, r0, #CACHE_DLINESIZE |
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cmp r0, r1 |
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blo 1b |
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#endif |
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mcr p15, 0, r0, c7, c10, 4 @ drain WB |
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ret lr |
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/* |
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* dma_flush_range(start, end) |
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* |
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* Clean and invalidate the specified virtual address range. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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* |
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* (same as arm926) |
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*/ |
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ENTRY(arm946_dma_flush_range) |
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bic r0, r0, #CACHE_DLINESIZE - 1 |
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1: |
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
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mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
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#else |
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
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#endif |
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add r0, r0, #CACHE_DLINESIZE |
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cmp r0, r1 |
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blo 1b |
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mcr p15, 0, r0, c7, c10, 4 @ drain WB |
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ret lr |
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/* |
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* dma_map_area(start, size, dir) |
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* - start - kernel virtual start address |
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* - size - size of region |
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* - dir - DMA direction |
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*/ |
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ENTRY(arm946_dma_map_area) |
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add r1, r1, r0 |
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cmp r2, #DMA_TO_DEVICE |
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beq arm946_dma_clean_range |
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bcs arm946_dma_inv_range |
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b arm946_dma_flush_range |
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ENDPROC(arm946_dma_map_area) |
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/* |
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* dma_unmap_area(start, size, dir) |
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* - start - kernel virtual start address |
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* - size - size of region |
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* - dir - DMA direction |
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*/ |
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ENTRY(arm946_dma_unmap_area) |
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ret lr |
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ENDPROC(arm946_dma_unmap_area) |
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.globl arm946_flush_kern_cache_louis |
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.equ arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all |
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) |
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define_cache_functions arm946 |
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ENTRY(cpu_arm946_dcache_clean_area) |
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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add r0, r0, #CACHE_DLINESIZE |
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subs r1, r1, #CACHE_DLINESIZE |
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bhi 1b |
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#endif |
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mcr p15, 0, r0, c7, c10, 4 @ drain WB |
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ret lr |
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.type __arm946_setup, #function |
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__arm946_setup: |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache |
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mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache |
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mcr p15, 0, r0, c7, c10, 4 @ drain WB |
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mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7 |
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mcr p15, 0, r0, c6, c4, 0 |
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mcr p15, 0, r0, c6, c5, 0 |
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mcr p15, 0, r0, c6, c6, 0 |
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mcr p15, 0, r0, c6, c7, 0 |
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mov r0, #0x0000003F @ base = 0, size = 4GB |
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mcr p15, 0, r0, c6, c0, 0 @ set region 0, default |
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM |
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ldr r7, =CONFIG_DRAM_SIZE @ size of RAM (must be >= 4KB) |
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pr_val r3, r0, r7, #1 |
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mcr p15, 0, r3, c6, c1, 0 |
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ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH |
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ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB) |
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pr_val r3, r0, r7, #1 |
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mcr p15, 0, r3, c6, c2, 0 |
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mov r0, #0x06 |
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mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable |
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mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable |
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH |
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mov r0, #0x00 @ disable whole write buffer |
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#else |
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mov r0, #0x02 @ region 1 write bufferred |
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#endif |
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mcr p15, 0, r0, c3, c0, 0 |
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/* |
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* Access Permission Settings for future permission control by PU. |
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* |
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* priv. user |
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* region 0 (whole) rw -- : b0001 |
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* region 1 (RAM) rw rw : b0011 |
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* region 2 (FLASH) rw r- : b0010 |
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* region 3~7 (none) -- -- : b0000 |
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*/ |
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mov r0, #0x00000031 |
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orr r0, r0, #0x00000200 |
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mcr p15, 0, r0, c5, c0, 2 @ set data access permission |
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mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission |
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mrc p15, 0, r0, c1, c0 @ get control register |
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orr r0, r0, #0x00001000 @ I-cache |
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orr r0, r0, #0x00000005 @ MPU/D-cache |
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#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN |
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orr r0, r0, #0x00004000 @ .1.. .... .... .... |
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#endif |
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ret lr |
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.size __arm946_setup, . - __arm946_setup |
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__INITDATA |
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
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define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1 |
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.section ".rodata" |
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string cpu_arch_name, "armv5te" |
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string cpu_elf_name, "v5t" |
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string cpu_arm946_name, "ARM946E-S" |
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.align |
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.section ".proc.info.init", "a" |
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.type __arm946_proc_info,#object |
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__arm946_proc_info: |
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.long 0x41009460 |
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.long 0xff00fff0 |
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.long 0 |
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.long 0 |
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initfn __arm946_setup, __arm946_proc_info |
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.long cpu_arch_name |
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.long cpu_elf_name |
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB |
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.long cpu_arm946_name |
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.long arm946_processor_functions |
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.long 0 |
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.long 0 |
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.long arm946_cache_fns |
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.size __arm946_proc_info, . - __arm946_proc_info |
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