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243 lines
5.6 KiB
243 lines
5.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* linux/arch/arm/mm/nommu.c |
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* |
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* ARM uCLinux supporting functions. |
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*/ |
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#include <linux/module.h> |
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#include <linux/mm.h> |
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#include <linux/pagemap.h> |
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#include <linux/io.h> |
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#include <linux/memblock.h> |
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#include <linux/kernel.h> |
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#include <asm/cacheflush.h> |
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#include <asm/cp15.h> |
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#include <asm/sections.h> |
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#include <asm/page.h> |
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#include <asm/setup.h> |
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#include <asm/traps.h> |
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#include <asm/mach/arch.h> |
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#include <asm/cputype.h> |
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#include <asm/mpu.h> |
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#include <asm/procinfo.h> |
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#include "mm.h" |
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unsigned long vectors_base; |
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#ifdef CONFIG_ARM_MPU |
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struct mpu_rgn_info mpu_rgn_info; |
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#endif |
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#ifdef CONFIG_CPU_CP15 |
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#ifdef CONFIG_CPU_HIGH_VECTOR |
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unsigned long setup_vectors_base(void) |
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{ |
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unsigned long reg = get_cr(); |
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set_cr(reg | CR_V); |
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return 0xffff0000; |
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} |
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#else /* CONFIG_CPU_HIGH_VECTOR */ |
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/* Write exception base address to VBAR */ |
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static inline void set_vbar(unsigned long val) |
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{ |
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asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc"); |
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} |
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/* |
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* Security extensions, bits[7:4], permitted values, |
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* 0b0000 - not implemented, 0b0001/0b0010 - implemented |
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*/ |
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static inline bool security_extensions_enabled(void) |
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{ |
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/* Check CPUID Identification Scheme before ID_PFR1 read */ |
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if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) |
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return cpuid_feature_extract(CPUID_EXT_PFR1, 4) || |
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cpuid_feature_extract(CPUID_EXT_PFR1, 20); |
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return 0; |
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} |
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unsigned long setup_vectors_base(void) |
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{ |
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unsigned long base = 0, reg = get_cr(); |
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set_cr(reg & ~CR_V); |
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if (security_extensions_enabled()) { |
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if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) |
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base = CONFIG_DRAM_BASE; |
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set_vbar(base); |
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} else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) { |
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if (CONFIG_DRAM_BASE != 0) |
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pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n"); |
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} |
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return base; |
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} |
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#endif /* CONFIG_CPU_HIGH_VECTOR */ |
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#endif /* CONFIG_CPU_CP15 */ |
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void __init arm_mm_memblock_reserve(void) |
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{ |
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#ifndef CONFIG_CPU_V7M |
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vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0; |
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/* |
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* Register the exception vector page. |
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* some architectures which the DRAM is the exception vector to trap, |
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* alloc_page breaks with error, although it is not NULL, but "0." |
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*/ |
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memblock_reserve(vectors_base, 2 * PAGE_SIZE); |
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#else /* ifndef CONFIG_CPU_V7M */ |
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/* |
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* There is no dedicated vector page on V7-M. So nothing needs to be |
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* reserved here. |
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*/ |
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#endif |
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/* |
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* In any case, always ensure address 0 is never used as many things |
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* get very confused if 0 is returned as a legitimate address. |
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*/ |
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memblock_reserve(0, 1); |
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} |
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static void __init adjust_lowmem_bounds_mpu(void) |
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{ |
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unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA; |
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switch (pmsa) { |
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case MMFR0_PMSAv7: |
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pmsav7_adjust_lowmem_bounds(); |
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break; |
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case MMFR0_PMSAv8: |
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pmsav8_adjust_lowmem_bounds(); |
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break; |
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default: |
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break; |
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} |
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} |
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static void __init mpu_setup(void) |
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{ |
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unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA; |
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switch (pmsa) { |
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case MMFR0_PMSAv7: |
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pmsav7_setup(); |
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break; |
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case MMFR0_PMSAv8: |
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pmsav8_setup(); |
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break; |
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default: |
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break; |
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} |
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} |
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void __init adjust_lowmem_bounds(void) |
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{ |
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phys_addr_t end; |
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adjust_lowmem_bounds_mpu(); |
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end = memblock_end_of_DRAM(); |
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high_memory = __va(end - 1) + 1; |
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memblock_set_current_limit(end); |
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} |
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/* |
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* paging_init() sets up the page tables, initialises the zone memory |
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* maps, and sets up the zero page, bad page and bad page tables. |
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*/ |
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void __init paging_init(const struct machine_desc *mdesc) |
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{ |
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early_trap_init((void *)vectors_base); |
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mpu_setup(); |
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bootmem_init(); |
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} |
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/* |
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* We don't need to do anything here for nommu machines. |
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*/ |
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void setup_mm_for_reboot(void) |
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{ |
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} |
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void flush_dcache_page(struct page *page) |
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{ |
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__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); |
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} |
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EXPORT_SYMBOL(flush_dcache_page); |
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page, |
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unsigned long uaddr, void *dst, const void *src, |
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unsigned long len) |
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{ |
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memcpy(dst, src, len); |
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if (vma->vm_flags & VM_EXEC) |
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__cpuc_coherent_user_range(uaddr, uaddr + len); |
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} |
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void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, |
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size_t size, unsigned int mtype) |
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{ |
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if (pfn >= (0x100000000ULL >> PAGE_SHIFT)) |
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return NULL; |
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return (void __iomem *) (offset + (pfn << PAGE_SHIFT)); |
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} |
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EXPORT_SYMBOL(__arm_ioremap_pfn); |
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void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size, |
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unsigned int mtype, void *caller) |
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{ |
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return (void __iomem *)phys_addr; |
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} |
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void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *); |
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void __iomem *ioremap(resource_size_t res_cookie, size_t size) |
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{ |
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return __arm_ioremap_caller(res_cookie, size, MT_DEVICE, |
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__builtin_return_address(0)); |
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} |
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EXPORT_SYMBOL(ioremap); |
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void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size) |
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{ |
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return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED, |
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__builtin_return_address(0)); |
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} |
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EXPORT_SYMBOL(ioremap_cache); |
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void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) |
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{ |
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return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC, |
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__builtin_return_address(0)); |
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} |
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EXPORT_SYMBOL(ioremap_wc); |
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#ifdef CONFIG_PCI |
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#include <asm/mach/map.h> |
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void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size) |
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{ |
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return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, |
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__builtin_return_address(0)); |
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} |
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EXPORT_SYMBOL_GPL(pci_remap_cfgspace); |
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#endif |
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void *arch_memremap_wb(phys_addr_t phys_addr, size_t size) |
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{ |
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return (void *)phys_addr; |
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} |
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void __iounmap(volatile void __iomem *addr) |
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{ |
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} |
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EXPORT_SYMBOL(__iounmap); |
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void (*arch_iounmap)(volatile void __iomem *); |
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void iounmap(volatile void __iomem *addr) |
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{ |
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} |
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EXPORT_SYMBOL(iounmap);
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