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172 lines
4.6 KiB
172 lines
4.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block |
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* |
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* Created by: Nicolas Pitre, May 2012 |
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* Copyright: (C) 2012-2013 Linaro Limited |
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*/ |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/io.h> |
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#include <linux/errno.h> |
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#include <linux/of_address.h> |
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#include <linux/vexpress.h> |
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#include <linux/arm-cci.h> |
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#include <asm/mcpm.h> |
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#include <asm/proc-fns.h> |
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#include <asm/cacheflush.h> |
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#include <asm/cputype.h> |
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#include <asm/cp15.h> |
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#include "core.h" |
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#define RST_HOLD0 0x0 |
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#define RST_HOLD1 0x4 |
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#define SYS_SWRESET 0x8 |
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#define RST_STAT0 0xc |
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#define RST_STAT1 0x10 |
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#define EAG_CFG_R 0x20 |
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#define EAG_CFG_W 0x24 |
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#define KFC_CFG_R 0x28 |
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#define KFC_CFG_W 0x2c |
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#define DCS_CFG_R 0x30 |
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static void __iomem *dcscb_base; |
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static int dcscb_allcpus_mask[2]; |
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static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster) |
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{ |
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unsigned int rst_hold, cpumask = (1 << cpu); |
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); |
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if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster])) |
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return -EINVAL; |
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); |
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rst_hold &= ~(cpumask | (cpumask << 4)); |
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); |
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return 0; |
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} |
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static int dcscb_cluster_powerup(unsigned int cluster) |
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{ |
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unsigned int rst_hold; |
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pr_debug("%s: cluster %u\n", __func__, cluster); |
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if (cluster >= 2) |
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return -EINVAL; |
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/* remove cluster reset and add individual CPU's reset */ |
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); |
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rst_hold &= ~(1 << 8); |
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rst_hold |= dcscb_allcpus_mask[cluster]; |
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); |
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return 0; |
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} |
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static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) |
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{ |
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unsigned int rst_hold; |
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); |
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BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster])); |
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); |
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rst_hold |= (1 << cpu); |
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); |
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} |
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static void dcscb_cluster_powerdown_prepare(unsigned int cluster) |
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{ |
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unsigned int rst_hold; |
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pr_debug("%s: cluster %u\n", __func__, cluster); |
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BUG_ON(cluster >= 2); |
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rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); |
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rst_hold |= (1 << 8); |
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writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); |
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} |
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static void dcscb_cpu_cache_disable(void) |
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{ |
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/* Disable and flush the local CPU cache. */ |
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v7_exit_coherency_flush(louis); |
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} |
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static void dcscb_cluster_cache_disable(void) |
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{ |
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/* Flush all cache levels for this cluster. */ |
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v7_exit_coherency_flush(all); |
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/* |
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* A full outer cache flush could be needed at this point |
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* on platforms with such a cache, depending on where the |
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* outer cache sits. In some cases the notion of a "last |
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* cluster standing" would need to be implemented if the |
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* outer cache is shared across clusters. In any case, when |
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* the outer cache needs flushing, there is no concurrent |
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* access to the cache controller to worry about and no |
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* special locking besides what is already provided by the |
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* MCPM state machinery is needed. |
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*/ |
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/* |
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* Disable cluster-level coherency by masking |
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* incoming snoops and DVM messages: |
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*/ |
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cci_disable_port_by_cpu(read_cpuid_mpidr()); |
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} |
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static const struct mcpm_platform_ops dcscb_power_ops = { |
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.cpu_powerup = dcscb_cpu_powerup, |
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.cluster_powerup = dcscb_cluster_powerup, |
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.cpu_powerdown_prepare = dcscb_cpu_powerdown_prepare, |
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.cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare, |
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.cpu_cache_disable = dcscb_cpu_cache_disable, |
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.cluster_cache_disable = dcscb_cluster_cache_disable, |
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}; |
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extern void dcscb_power_up_setup(unsigned int affinity_level); |
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static int __init dcscb_init(void) |
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{ |
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struct device_node *node; |
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unsigned int cfg; |
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int ret; |
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if (!cci_probed()) |
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return -ENODEV; |
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node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb"); |
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if (!node) |
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return -ENODEV; |
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dcscb_base = of_iomap(node, 0); |
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if (!dcscb_base) |
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return -EADDRNOTAVAIL; |
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cfg = readl_relaxed(dcscb_base + DCS_CFG_R); |
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dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1; |
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dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1; |
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ret = mcpm_platform_register(&dcscb_power_ops); |
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if (!ret) |
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ret = mcpm_sync_init(dcscb_power_up_setup); |
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if (ret) { |
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iounmap(dcscb_base); |
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return ret; |
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} |
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pr_info("VExpress DCSCB support installed\n"); |
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/* |
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* Future entries into the kernel can now go |
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* through the cluster entry vectors. |
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*/ |
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vexpress_flags_set(__pa_symbol(mcpm_entry_point)); |
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return 0; |
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} |
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early_initcall(dcscb_init);
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