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171 lines
4.4 KiB
171 lines
4.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright Altera Corporation (C) 2016. All rights reserved. |
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*/ |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/genalloc.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include "core.h" |
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#define ALTR_OCRAM_CLEAR_ECC 0x00000018 |
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#define ALTR_OCRAM_ECC_EN 0x00000019 |
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void socfpga_init_ocram_ecc(void) |
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{ |
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struct device_node *np; |
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void __iomem *mapped_ocr_edac_addr; |
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/* Find the OCRAM EDAC device tree node */ |
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np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); |
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if (!np) { |
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pr_err("Unable to find socfpga-ocram-ecc\n"); |
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return; |
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} |
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mapped_ocr_edac_addr = of_iomap(np, 0); |
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of_node_put(np); |
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if (!mapped_ocr_edac_addr) { |
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pr_err("Unable to map OCRAM ecc regs.\n"); |
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return; |
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} |
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/* Clear any pending OCRAM ECC interrupts, then enable ECC */ |
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writel(ALTR_OCRAM_CLEAR_ECC, mapped_ocr_edac_addr); |
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writel(ALTR_OCRAM_ECC_EN, mapped_ocr_edac_addr); |
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iounmap(mapped_ocr_edac_addr); |
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} |
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/* Arria10 OCRAM Section */ |
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#define ALTR_A10_ECC_CTRL_OFST 0x08 |
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#define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0)) |
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#define ALTR_A10_ECC_INITA BIT(16) |
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#define ALTR_A10_ECC_INITSTAT_OFST 0x0C |
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#define ALTR_A10_ECC_INITCOMPLETEA BIT(0) |
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#define ALTR_A10_ECC_INITCOMPLETEB BIT(8) |
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#define ALTR_A10_ECC_ERRINTEN_OFST 0x10 |
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#define ALTR_A10_ECC_SERRINTEN BIT(0) |
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#define ALTR_A10_ECC_INTSTAT_OFST 0x20 |
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#define ALTR_A10_ECC_SERRPENA BIT(0) |
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#define ALTR_A10_ECC_DERRPENA BIT(8) |
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#define ALTR_A10_ECC_ERRPENA_MASK (ALTR_A10_ECC_SERRPENA | \ |
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ALTR_A10_ECC_DERRPENA) |
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/* ECC Manager Defines */ |
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#define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94 |
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#define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98 |
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#define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1) |
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#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000 |
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static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) |
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{ |
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u32 value = readl(ioaddr); |
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value |= bit_mask; |
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writel(value, ioaddr); |
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} |
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static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) |
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{ |
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u32 value = readl(ioaddr); |
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value &= ~bit_mask; |
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writel(value, ioaddr); |
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} |
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static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) |
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{ |
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u32 value = readl(ioaddr); |
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return (value & bit_mask) ? 1 : 0; |
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} |
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/* |
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* This function uses the memory initialization block in the Arria10 ECC |
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* controller to initialize/clear the entire memory data and ECC data. |
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*/ |
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static int altr_init_memory_port(void __iomem *ioaddr) |
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{ |
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int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; |
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ecc_set_bits(ALTR_A10_ECC_INITA, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); |
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while (limit--) { |
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if (ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA, |
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(ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) |
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break; |
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udelay(1); |
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} |
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if (limit < 0) |
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return -EBUSY; |
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/* Clear any pending ECC interrupts */ |
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writel(ALTR_A10_ECC_ERRPENA_MASK, |
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(ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); |
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return 0; |
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} |
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void socfpga_init_arria10_ocram_ecc(void) |
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{ |
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struct device_node *np; |
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int ret = 0; |
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void __iomem *ecc_block_base; |
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if (!sys_manager_base_addr) { |
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pr_err("SOCFPGA: sys-mgr is not initialized\n"); |
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return; |
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} |
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/* Find the OCRAM EDAC device tree node */ |
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np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-ocram-ecc"); |
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if (!np) { |
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pr_err("Unable to find socfpga-a10-ocram-ecc\n"); |
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return; |
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} |
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/* Map the ECC Block */ |
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ecc_block_base = of_iomap(np, 0); |
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of_node_put(np); |
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if (!ecc_block_base) { |
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pr_err("Unable to map OCRAM ECC block\n"); |
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return; |
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} |
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/* Disable ECC */ |
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writel(ALTR_A10_OCRAM_ECC_EN_CTL, |
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sys_manager_base_addr + A10_SYSMGR_ECC_INTMASK_SET_OFST); |
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ecc_clear_bits(ALTR_A10_ECC_SERRINTEN, |
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(ecc_block_base + ALTR_A10_ECC_ERRINTEN_OFST)); |
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ecc_clear_bits(ALTR_A10_OCRAM_ECC_EN_CTL, |
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(ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); |
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/* Ensure all writes complete */ |
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wmb(); |
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/* Use HW initialization block to initialize memory for ECC */ |
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ret = altr_init_memory_port(ecc_block_base); |
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if (ret) { |
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pr_err("ECC: cannot init OCRAM PORTA memory\n"); |
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goto exit; |
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} |
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/* Enable ECC */ |
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ecc_set_bits(ALTR_A10_OCRAM_ECC_EN_CTL, |
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(ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); |
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ecc_set_bits(ALTR_A10_ECC_SERRINTEN, |
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(ecc_block_base + ALTR_A10_ECC_ERRINTEN_OFST)); |
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writel(ALTR_A10_OCRAM_ECC_EN_CTL, |
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sys_manager_base_addr + A10_SYSMGR_ECC_INTMASK_CLR_OFST); |
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/* Ensure all writes complete */ |
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wmb(); |
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exit: |
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iounmap(ecc_block_base); |
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}
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