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82 lines
2.2 KiB
82 lines
2.2 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* arch/arm/mach-pxa/include/mach/zeus.h |
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* |
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* Author: David Vrabel |
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* Created: Sept 28, 2005 |
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* Copyright: Arcom Control Systems Ltd. |
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* |
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* Maintained by: Marc Zyngier <[email protected]> |
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*/ |
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#ifndef _MACH_ZEUS_H |
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#define _MACH_ZEUS_H |
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#define ZEUS_NR_IRQS (IRQ_BOARD_START + 48) |
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/* Physical addresses */ |
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#define ZEUS_FLASH_PHYS PXA_CS0_PHYS |
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#define ZEUS_ETH0_PHYS PXA_CS1_PHYS |
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#define ZEUS_ETH1_PHYS PXA_CS2_PHYS |
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#define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000) |
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#define ZEUS_SRAM_PHYS PXA_CS5_PHYS |
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#define ZEUS_PC104IO_PHYS (0x30000000) |
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#define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000) |
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#define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000) |
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#define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000) |
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#define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000) |
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/* GPIOs */ |
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#define ZEUS_AC97_GPIO 0 |
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#define ZEUS_WAKEUP_GPIO 1 |
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#define ZEUS_UARTA_GPIO 9 |
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#define ZEUS_UARTB_GPIO 10 |
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#define ZEUS_UARTC_GPIO 12 |
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#define ZEUS_UARTD_GPIO 11 |
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#define ZEUS_ETH0_GPIO 14 |
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#define ZEUS_ISA_GPIO 17 |
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#define ZEUS_BKLEN_GPIO 19 |
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#define ZEUS_USB2_PWREN_GPIO 22 |
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#define ZEUS_PTT_GPIO 27 |
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#define ZEUS_CF_CD_GPIO 35 |
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#define ZEUS_MMC_WP_GPIO 52 |
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#define ZEUS_MMC_CD_GPIO 53 |
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#define ZEUS_EXTGPIO_GPIO 91 |
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#define ZEUS_CF_PWEN_GPIO 97 |
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#define ZEUS_CF_RDY_GPIO 99 |
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#define ZEUS_LCD_EN_GPIO 101 |
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#define ZEUS_ETH1_GPIO 113 |
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#define ZEUS_CAN_GPIO 116 |
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#define ZEUS_EXT0_GPIO_BASE 128 |
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#define ZEUS_EXT1_GPIO_BASE 160 |
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#define ZEUS_USER_GPIO_BASE 192 |
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#define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x)) |
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#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) |
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#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) |
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#define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2) |
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/* |
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* CPLD registers: |
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* Only 4 registers, but spread over a 32MB address space. |
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* Be gentle, and remap that over 32kB... |
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*/ |
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#define ZEUS_CPLD IOMEM(0xf0000000) |
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#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) |
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#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) |
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#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) |
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/* CPLD register bits */ |
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#define ZEUS_CPLD_CONTROL_CF_RST 0x01 |
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#define ZEUS_PC104IO IOMEM(0xf1000000) |
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#define ZEUS_SRAM_SIZE (256 * 1024) |
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#endif |
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