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179 lines
4.5 KiB
179 lines
4.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* RTC I/O Bridge interfaces for CSR SiRFprimaII/atlas7 |
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* ARM access the registers of SYSRTC, GPSRTC and PWRC through this module |
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* |
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/regmap.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/of_platform.h> |
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#define SIRFSOC_CPUIOBRG_CTRL 0x00 |
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#define SIRFSOC_CPUIOBRG_WRBE 0x04 |
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#define SIRFSOC_CPUIOBRG_ADDR 0x08 |
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#define SIRFSOC_CPUIOBRG_DATA 0x0c |
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/* |
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* suspend asm codes will access this address to make system deepsleep |
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* after DRAM becomes self-refresh |
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*/ |
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void __iomem *sirfsoc_rtciobrg_base; |
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static DEFINE_SPINLOCK(rtciobrg_lock); |
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/* |
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* symbols without lock are only used by suspend asm codes |
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* and these symbols are not exported too |
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*/ |
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void sirfsoc_rtc_iobrg_wait_sync(void) |
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{ |
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while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL)) |
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cpu_relax(); |
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} |
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void sirfsoc_rtc_iobrg_besyncing(void) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&rtciobrg_lock, flags); |
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sirfsoc_rtc_iobrg_wait_sync(); |
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spin_unlock_irqrestore(&rtciobrg_lock, flags); |
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} |
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EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_besyncing); |
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u32 __sirfsoc_rtc_iobrg_readl(u32 addr) |
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{ |
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sirfsoc_rtc_iobrg_wait_sync(); |
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writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); |
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writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); |
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writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); |
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sirfsoc_rtc_iobrg_wait_sync(); |
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return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); |
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} |
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u32 sirfsoc_rtc_iobrg_readl(u32 addr) |
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{ |
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unsigned long flags, val; |
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/* TODO: add hwspinlock to sync with M3 */ |
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spin_lock_irqsave(&rtciobrg_lock, flags); |
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val = __sirfsoc_rtc_iobrg_readl(addr); |
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spin_unlock_irqrestore(&rtciobrg_lock, flags); |
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return val; |
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} |
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EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_readl); |
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void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr) |
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{ |
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sirfsoc_rtc_iobrg_wait_sync(); |
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writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); |
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writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); |
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writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); |
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} |
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void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr) |
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{ |
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unsigned long flags; |
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/* TODO: add hwspinlock to sync with M3 */ |
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spin_lock_irqsave(&rtciobrg_lock, flags); |
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sirfsoc_rtc_iobrg_pre_writel(val, addr); |
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writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); |
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sirfsoc_rtc_iobrg_wait_sync(); |
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spin_unlock_irqrestore(&rtciobrg_lock, flags); |
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} |
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EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel); |
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static int regmap_iobg_regwrite(void *context, unsigned int reg, |
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unsigned int val) |
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{ |
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sirfsoc_rtc_iobrg_writel(val, reg); |
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return 0; |
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} |
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static int regmap_iobg_regread(void *context, unsigned int reg, |
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unsigned int *val) |
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{ |
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*val = (u32)sirfsoc_rtc_iobrg_readl(reg); |
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return 0; |
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} |
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static struct regmap_bus regmap_iobg = { |
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.reg_write = regmap_iobg_regwrite, |
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.reg_read = regmap_iobg_regread, |
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}; |
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/** |
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* devm_regmap_init_iobg(): Initialise managed register map |
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* |
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* @iobg: Device that will be interacted with |
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* @config: Configuration for register map |
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* |
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* The return value will be an ERR_PTR() on error or a valid pointer |
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* to a struct regmap. The regmap will be automatically freed by the |
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* device management code. |
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*/ |
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struct regmap *devm_regmap_init_iobg(struct device *dev, |
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const struct regmap_config *config) |
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{ |
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const struct regmap_bus *bus = ®map_iobg; |
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return devm_regmap_init(dev, bus, dev, config); |
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} |
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EXPORT_SYMBOL_GPL(devm_regmap_init_iobg); |
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static const struct of_device_id rtciobrg_ids[] = { |
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{ .compatible = "sirf,prima2-rtciobg" }, |
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{} |
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}; |
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static int sirfsoc_rtciobrg_probe(struct platform_device *op) |
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{ |
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struct device_node *np = op->dev.of_node; |
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sirfsoc_rtciobrg_base = of_iomap(np, 0); |
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if (!sirfsoc_rtciobrg_base) |
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panic("unable to map rtc iobrg registers\n"); |
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return 0; |
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} |
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static struct platform_driver sirfsoc_rtciobrg_driver = { |
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.probe = sirfsoc_rtciobrg_probe, |
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.driver = { |
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.name = "sirfsoc-rtciobrg", |
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.of_match_table = rtciobrg_ids, |
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}, |
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}; |
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static int __init sirfsoc_rtciobrg_init(void) |
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{ |
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return platform_driver_register(&sirfsoc_rtciobrg_driver); |
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} |
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postcore_initcall(sirfsoc_rtciobrg_init); |
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MODULE_AUTHOR("Zhiwu Song <[email protected]>"); |
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MODULE_AUTHOR("Barry Song <[email protected]>"); |
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MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge"); |
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MODULE_LICENSE("GPL v2");
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