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281 lines
8.9 KiB
281 lines
8.9 KiB
/* |
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* arch/arm/mach-omap1/pm.h |
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* |
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* Header file for OMAP1 Power Management Routines |
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* |
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* Author: MontaVista Software, Inc. |
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* [email protected] |
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* |
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* Copyright 2002 MontaVista Software Inc. |
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* |
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* Cleanup 2004 for Linux 2.6 by Dirk Behme <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program; if not, write to the Free Software Foundation, Inc., |
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* 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#ifndef __ARCH_ARM_MACH_OMAP1_PM_H |
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#define __ARCH_ARM_MACH_OMAP1_PM_H |
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/* |
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* ---------------------------------------------------------------------------- |
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* Register and offset definitions to be used in PM assembler code |
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* ---------------------------------------------------------------------------- |
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*/ |
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#define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00) |
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#define ARM_IDLECT1_ASM_OFFSET 0x04 |
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#define ARM_IDLECT2_ASM_OFFSET 0x08 |
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#define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00) |
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#define EMIFS_CONFIG_ASM_OFFSET 0x0c |
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#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20 |
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/* |
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* ---------------------------------------------------------------------------- |
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* Power management bitmasks |
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* ---------------------------------------------------------------------------- |
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*/ |
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#define IDLE_WAIT_CYCLES 0x00000fff |
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#define PERIPHERAL_ENABLE 0x2 |
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#define SELF_REFRESH_MODE 0x0c000001 |
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#define IDLE_EMIFS_REQUEST 0xc |
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#define MODEM_32K_EN 0x1 |
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#define PER_EN 0x1 |
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#define CPU_SUSPEND_SIZE 200 |
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#define ULPD_LOW_PWR_EN 0x0001 |
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#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010 |
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#define ULPD_SETUP_ANALOG_CELL_3_VAL 0 |
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#define ULPD_POWER_CTRL_REG_VAL 0x0219 |
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#define DSP_IDLE_DELAY 10 |
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#define DSP_IDLE 0x0040 |
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#define DSP_RST 0x0004 |
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#define DSP_ENABLE 0x0002 |
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#define SUFFICIENT_DSP_RESET_TIME 1000 |
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#define DEFAULT_MPUI_CONFIG 0x05cf |
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#define ENABLE_XORCLK 0x2 |
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#define DSP_CLOCK_ENABLE 0x2000 |
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#define DSP_IDLE_MODE 0x2 |
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#define TC_IDLE_REQUEST (0x0000000c) |
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#define IRQ_LEVEL2 (1<<0) |
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#define IRQ_KEYBOARD (1<<1) |
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#define IRQ_UART2 (1<<15) |
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#define PDE_BIT 0x08 |
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#define PWD_EN_BIT 0x04 |
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#define EN_PERCK_BIT 0x04 |
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#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7 |
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#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5 |
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#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00 |
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#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2 |
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/* Both big sleep and deep sleep use same values. Difference is in ULPD. */ |
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#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7 |
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#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7 |
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#define OMAP1610_IDLECT3_VAL 0x3f |
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#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c |
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#define OMAP1610_IDLECT3 0xfffece24 |
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#define OMAP1610_IDLE_LOOP_REQUEST 0x0400 |
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#define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7 |
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#define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7 |
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#define OMAP7XX_IDLECT3_VAL 0x3f |
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#define OMAP7XX_IDLECT3 0xfffece24 |
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#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00 |
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#if !defined(CONFIG_ARCH_OMAP730) && \ |
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!defined(CONFIG_ARCH_OMAP850) && \ |
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!defined(CONFIG_ARCH_OMAP15XX) && \ |
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!defined(CONFIG_ARCH_OMAP16XX) |
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#warning "Power management for this processor not implemented yet" |
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#endif |
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#ifndef __ASSEMBLER__ |
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#include <linux/clk.h> |
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extern struct kset power_subsys; |
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extern void prevent_idle_sleep(void); |
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extern void allow_idle_sleep(void); |
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extern void omap1_pm_idle(void); |
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extern void omap1_pm_suspend(void); |
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extern void omap7xx_cpu_suspend(unsigned long, unsigned long); |
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extern void omap1510_cpu_suspend(unsigned long, unsigned long); |
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extern void omap1610_cpu_suspend(unsigned long, unsigned long); |
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extern void omap7xx_idle_loop_suspend(void); |
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extern void omap1510_idle_loop_suspend(void); |
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extern void omap1610_idle_loop_suspend(void); |
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extern unsigned int omap7xx_cpu_suspend_sz; |
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extern unsigned int omap1510_cpu_suspend_sz; |
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extern unsigned int omap1610_cpu_suspend_sz; |
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extern unsigned int omap7xx_idle_loop_suspend_sz; |
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extern unsigned int omap1510_idle_loop_suspend_sz; |
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extern unsigned int omap1610_idle_loop_suspend_sz; |
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#ifdef CONFIG_OMAP_SERIAL_WAKE |
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extern void omap_serial_wake_trigger(int enable); |
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#else |
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#define omap_serial_wakeup_init() {} |
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#define omap_serial_wake_trigger(x) {} |
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#endif /* CONFIG_OMAP_SERIAL_WAKE */ |
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#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x) |
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#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x)) |
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#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] |
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#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x) |
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#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x)) |
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#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] |
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#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) |
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#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) |
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#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] |
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#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x) |
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#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x)) |
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#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] |
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#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) |
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#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) |
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#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] |
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#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x) |
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#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x)) |
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#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] |
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/* |
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* List of global OMAP registers to preserve. |
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* More ones like CP and general purpose register values are preserved |
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* with the stack pointer in sleep.S. |
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*/ |
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enum arm_save_state { |
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ARM_SLEEP_SAVE_START = 0, |
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/* |
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* MPU control registers 32 bits |
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*/ |
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ARM_SLEEP_SAVE_ARM_CKCTL, |
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ARM_SLEEP_SAVE_ARM_IDLECT1, |
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ARM_SLEEP_SAVE_ARM_IDLECT2, |
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ARM_SLEEP_SAVE_ARM_IDLECT3, |
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ARM_SLEEP_SAVE_ARM_EWUPCT, |
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ARM_SLEEP_SAVE_ARM_RSTCT1, |
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ARM_SLEEP_SAVE_ARM_RSTCT2, |
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ARM_SLEEP_SAVE_ARM_SYSST, |
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ARM_SLEEP_SAVE_SIZE |
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}; |
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enum dsp_save_state { |
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DSP_SLEEP_SAVE_START = 0, |
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/* |
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* DSP registers 16 bits |
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*/ |
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DSP_SLEEP_SAVE_DSP_IDLECT2, |
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DSP_SLEEP_SAVE_SIZE |
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}; |
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enum ulpd_save_state { |
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ULPD_SLEEP_SAVE_START = 0, |
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/* |
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* ULPD registers 16 bits |
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*/ |
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ULPD_SLEEP_SAVE_ULPD_IT_STATUS, |
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ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL, |
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ULPD_SLEEP_SAVE_ULPD_SOFT_REQ, |
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ULPD_SLEEP_SAVE_ULPD_STATUS_REQ, |
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ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL, |
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ULPD_SLEEP_SAVE_ULPD_POWER_CTRL, |
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ULPD_SLEEP_SAVE_SIZE |
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}; |
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enum mpui1510_save_state { |
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MPUI1510_SLEEP_SAVE_START = 0, |
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/* |
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* MPUI registers 32 bits |
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*/ |
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MPUI1510_SLEEP_SAVE_MPUI_CTRL, |
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MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, |
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MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG, |
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MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS, |
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MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, |
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MPUI1510_SLEEP_SAVE_EMIFS_CONFIG, |
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MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR, |
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MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR, |
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#if defined(CONFIG_ARCH_OMAP15XX) |
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MPUI1510_SLEEP_SAVE_SIZE |
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#else |
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MPUI1510_SLEEP_SAVE_SIZE = 0 |
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#endif |
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}; |
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enum mpui7xx_save_state { |
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MPUI7XX_SLEEP_SAVE_START = 0, |
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/* |
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* MPUI registers 32 bits |
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*/ |
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MPUI7XX_SLEEP_SAVE_MPUI_CTRL, |
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MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, |
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MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG, |
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MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS, |
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MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, |
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MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG, |
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MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR, |
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MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR, |
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MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR, |
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#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
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MPUI7XX_SLEEP_SAVE_SIZE |
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#else |
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MPUI7XX_SLEEP_SAVE_SIZE = 0 |
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#endif |
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}; |
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enum mpui1610_save_state { |
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MPUI1610_SLEEP_SAVE_START = 0, |
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/* |
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* MPUI registers 32 bits |
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*/ |
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MPUI1610_SLEEP_SAVE_MPUI_CTRL, |
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MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, |
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MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG, |
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MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS, |
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MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, |
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MPUI1610_SLEEP_SAVE_EMIFS_CONFIG, |
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MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR, |
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MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR, |
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MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR, |
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MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR, |
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MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR, |
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#if defined(CONFIG_ARCH_OMAP16XX) |
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MPUI1610_SLEEP_SAVE_SIZE |
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#else |
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MPUI1610_SLEEP_SAVE_SIZE = 0 |
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#endif |
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}; |
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#endif /* ASSEMBLER */ |
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#endif /* __ASM_ARCH_OMAP_PM_H */
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