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440 lines
9.3 KiB
440 lines
9.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/arm/mach-ebsa110/isamem.c |
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* |
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* Copyright (C) 2001 Russell King |
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* |
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* Perform "ISA" memory and IO accesses. The EBSA110 has some "peculiarities" |
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* in the way it handles accesses to odd IO ports on 16-bit devices. These |
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* devices have their D0-D15 lines connected to the processors D0-D15 lines. |
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* Since they expect all byte IO operations to be performed on D0-D7, and the |
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* StrongARM expects to transfer the byte to these odd addresses on D8-D15, |
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* we must use a trick to get the required behaviour. |
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* |
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* The trick employed here is to use long word stores to odd address -1. The |
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* glue logic picks this up as a "trick" access, and asserts the LSB of the |
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* peripherals address bus, thereby accessing the odd IO port. Meanwhile, the |
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* StrongARM transfers its data on D0-D7 as expected. |
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* |
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* Things get more interesting on the pass-1 EBSA110 - the PCMCIA controller |
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* wiring was screwed in such a way that it had limited memory space access. |
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* Luckily, the work-around for this is not too horrible. See |
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* __isamem_convert_addr for the details. |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/io.h> |
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#include <mach/hardware.h> |
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#include <asm/page.h> |
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static void __iomem *__isamem_convert_addr(const volatile void __iomem *addr) |
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{ |
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u32 ret, a = (u32 __force) addr; |
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/* |
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* The PCMCIA controller is wired up as follows: |
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* +---------+---------+---------+---------+---------+---------+ |
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* PCMCIA | 2 2 2 2 | 1 1 1 1 | 1 1 1 1 | 1 1 | | | |
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* | 3 2 1 0 | 9 8 7 6 | 5 4 3 2 | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 | |
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* +---------+---------+---------+---------+---------+---------+ |
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* CPU | 2 2 2 2 | 2 1 1 1 | 1 1 1 1 | 1 1 1 | | | |
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* | 4 3 2 1 | 0 9 9 8 | 7 6 5 4 | 3 2 0 9 | 8 7 6 5 | 4 3 2 x | |
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* +---------+---------+---------+---------+---------+---------+ |
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* |
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* This means that we can access PCMCIA regions as follows: |
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* 0x*10000 -> 0x*1ffff |
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* 0x*70000 -> 0x*7ffff |
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* 0x*90000 -> 0x*9ffff |
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* 0x*f0000 -> 0x*fffff |
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*/ |
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ret = (a & 0xf803fe) << 1; |
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ret |= (a & 0x03fc00) << 2; |
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ret += 0xe8000000; |
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if ((a & 0x20000) == (a & 0x40000) >> 1) |
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return (void __iomem *)ret; |
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BUG(); |
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return NULL; |
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} |
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/* |
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* read[bwl] and write[bwl] |
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*/ |
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u8 __readb(const volatile void __iomem *addr) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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u32 ret; |
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if ((unsigned long)addr & 1) |
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ret = __raw_readl(a); |
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else |
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ret = __raw_readb(a); |
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return ret; |
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} |
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u16 __readw(const volatile void __iomem *addr) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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if ((unsigned long)addr & 1) |
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BUG(); |
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return __raw_readw(a); |
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} |
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u32 __readl(const volatile void __iomem *addr) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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u32 ret; |
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if ((unsigned long)addr & 3) |
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BUG(); |
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ret = __raw_readw(a); |
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ret |= __raw_readw(a + 4) << 16; |
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return ret; |
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} |
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EXPORT_SYMBOL(__readb); |
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EXPORT_SYMBOL(__readw); |
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EXPORT_SYMBOL(__readl); |
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void readsw(const volatile void __iomem *addr, void *data, int len) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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BUG_ON((unsigned long)addr & 1); |
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__raw_readsw(a, data, len); |
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} |
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EXPORT_SYMBOL(readsw); |
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void readsl(const volatile void __iomem *addr, void *data, int len) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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BUG_ON((unsigned long)addr & 3); |
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__raw_readsl(a, data, len); |
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} |
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EXPORT_SYMBOL(readsl); |
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void __writeb(u8 val, volatile void __iomem *addr) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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if ((unsigned long)addr & 1) |
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__raw_writel(val, a); |
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else |
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__raw_writeb(val, a); |
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} |
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void __writew(u16 val, volatile void __iomem *addr) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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if ((unsigned long)addr & 1) |
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BUG(); |
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__raw_writew(val, a); |
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} |
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void __writel(u32 val, volatile void __iomem *addr) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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if ((unsigned long)addr & 3) |
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BUG(); |
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__raw_writew(val, a); |
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__raw_writew(val >> 16, a + 4); |
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} |
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EXPORT_SYMBOL(__writeb); |
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EXPORT_SYMBOL(__writew); |
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EXPORT_SYMBOL(__writel); |
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void writesw(volatile void __iomem *addr, const void *data, int len) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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BUG_ON((unsigned long)addr & 1); |
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__raw_writesw(a, data, len); |
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} |
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EXPORT_SYMBOL(writesw); |
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void writesl(volatile void __iomem *addr, const void *data, int len) |
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{ |
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void __iomem *a = __isamem_convert_addr(addr); |
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BUG_ON((unsigned long)addr & 3); |
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__raw_writesl(a, data, len); |
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} |
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EXPORT_SYMBOL(writesl); |
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/* |
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* The EBSA110 has a weird "ISA IO" region: |
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* |
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* Region 0 (addr = 0xf0000000 + io << 2) |
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* -------------------------------------------------------- |
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* Physical region IO region |
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* f0000fe0 - f0000ffc 3f8 - 3ff ttyS0 |
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* f0000e60 - f0000e64 398 - 399 |
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* f0000de0 - f0000dfc 378 - 37f lp0 |
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* f0000be0 - f0000bfc 2f8 - 2ff ttyS1 |
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* |
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* Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1)) |
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* -------------------------------------------------------- |
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* Physical region IO region |
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* f00014f1 a79 pnp write data |
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* f00007c0 - f00007c1 3e0 - 3e1 pcmcia |
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* f00004f1 279 pnp address |
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* f0000440 - f000046c 220 - 236 eth0 |
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* f0000405 203 pnp read data |
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*/ |
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#define SUPERIO_PORT(p) \ |
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(((p) >> 3) == (0x3f8 >> 3) || \ |
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((p) >> 3) == (0x2f8 >> 3) || \ |
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((p) >> 3) == (0x378 >> 3)) |
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/* |
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* We're addressing an 8 or 16-bit peripheral which tranfers |
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* odd addresses on the low ISA byte lane. |
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*/ |
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u8 __inb8(unsigned int port) |
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{ |
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u32 ret; |
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/* |
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* The SuperIO registers use sane addressing techniques... |
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*/ |
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if (SUPERIO_PORT(port)) |
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ret = __raw_readb((void __iomem *)ISAIO_BASE + (port << 2)); |
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else { |
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void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); |
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/* |
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* Shame nothing else does |
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*/ |
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if (port & 1) |
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ret = __raw_readl(a); |
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else |
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ret = __raw_readb(a); |
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} |
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return ret; |
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} |
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/* |
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* We're addressing a 16-bit peripheral which transfers odd |
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* addresses on the high ISA byte lane. |
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*/ |
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u8 __inb16(unsigned int port) |
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{ |
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unsigned int offset; |
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/* |
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* The SuperIO registers use sane addressing techniques... |
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*/ |
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if (SUPERIO_PORT(port)) |
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offset = port << 2; |
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else |
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offset = (port & ~1) << 1 | (port & 1); |
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return __raw_readb((void __iomem *)ISAIO_BASE + offset); |
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} |
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u16 __inw(unsigned int port) |
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{ |
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unsigned int offset; |
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/* |
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* The SuperIO registers use sane addressing techniques... |
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*/ |
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if (SUPERIO_PORT(port)) |
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offset = port << 2; |
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else { |
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offset = port << 1; |
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BUG_ON(port & 1); |
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} |
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return __raw_readw((void __iomem *)ISAIO_BASE + offset); |
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} |
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/* |
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* Fake a 32-bit read with two 16-bit reads. Needed for 3c589. |
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*/ |
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u32 __inl(unsigned int port) |
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{ |
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void __iomem *a; |
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if (SUPERIO_PORT(port) || port & 3) |
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BUG(); |
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a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); |
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return __raw_readw(a) | __raw_readw(a + 4) << 16; |
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} |
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EXPORT_SYMBOL(__inb8); |
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EXPORT_SYMBOL(__inb16); |
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EXPORT_SYMBOL(__inw); |
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EXPORT_SYMBOL(__inl); |
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void __outb8(u8 val, unsigned int port) |
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{ |
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/* |
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* The SuperIO registers use sane addressing techniques... |
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*/ |
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if (SUPERIO_PORT(port)) |
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__raw_writeb(val, (void __iomem *)ISAIO_BASE + (port << 2)); |
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else { |
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void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); |
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/* |
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* Shame nothing else does |
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*/ |
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if (port & 1) |
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__raw_writel(val, a); |
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else |
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__raw_writeb(val, a); |
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} |
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} |
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void __outb16(u8 val, unsigned int port) |
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{ |
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unsigned int offset; |
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/* |
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* The SuperIO registers use sane addressing techniques... |
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*/ |
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if (SUPERIO_PORT(port)) |
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offset = port << 2; |
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else |
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offset = (port & ~1) << 1 | (port & 1); |
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__raw_writeb(val, (void __iomem *)ISAIO_BASE + offset); |
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} |
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void __outw(u16 val, unsigned int port) |
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{ |
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unsigned int offset; |
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/* |
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* The SuperIO registers use sane addressing techniques... |
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*/ |
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if (SUPERIO_PORT(port)) |
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offset = port << 2; |
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else { |
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offset = port << 1; |
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BUG_ON(port & 1); |
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} |
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__raw_writew(val, (void __iomem *)ISAIO_BASE + offset); |
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} |
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void __outl(u32 val, unsigned int port) |
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{ |
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BUG(); |
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} |
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EXPORT_SYMBOL(__outb8); |
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EXPORT_SYMBOL(__outb16); |
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EXPORT_SYMBOL(__outw); |
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EXPORT_SYMBOL(__outl); |
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void outsb(unsigned int port, const void *from, int len) |
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{ |
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u32 off; |
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if (SUPERIO_PORT(port)) |
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off = port << 2; |
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else { |
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off = (port & ~1) << 1; |
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if (port & 1) |
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BUG(); |
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} |
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__raw_writesb((void __iomem *)ISAIO_BASE + off, from, len); |
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} |
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void insb(unsigned int port, void *from, int len) |
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{ |
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u32 off; |
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if (SUPERIO_PORT(port)) |
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off = port << 2; |
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else { |
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off = (port & ~1) << 1; |
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if (port & 1) |
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BUG(); |
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} |
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__raw_readsb((void __iomem *)ISAIO_BASE + off, from, len); |
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} |
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EXPORT_SYMBOL(outsb); |
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EXPORT_SYMBOL(insb); |
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void outsw(unsigned int port, const void *from, int len) |
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{ |
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u32 off; |
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if (SUPERIO_PORT(port)) |
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off = port << 2; |
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else { |
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off = (port & ~1) << 1; |
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if (port & 1) |
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BUG(); |
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} |
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__raw_writesw((void __iomem *)ISAIO_BASE + off, from, len); |
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} |
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void insw(unsigned int port, void *from, int len) |
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{ |
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u32 off; |
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if (SUPERIO_PORT(port)) |
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off = port << 2; |
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else { |
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off = (port & ~1) << 1; |
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if (port & 1) |
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BUG(); |
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} |
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__raw_readsw((void __iomem *)ISAIO_BASE + off, from, len); |
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} |
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EXPORT_SYMBOL(outsw); |
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EXPORT_SYMBOL(insw); |
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/* |
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* We implement these as 16-bit insw/outsw, mainly for |
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* 3c589 cards. |
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*/ |
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void outsl(unsigned int port, const void *from, int len) |
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{ |
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u32 off = port << 1; |
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if (SUPERIO_PORT(port) || port & 3) |
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BUG(); |
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__raw_writesw((void __iomem *)ISAIO_BASE + off, from, len << 1); |
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} |
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void insl(unsigned int port, void *from, int len) |
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{ |
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u32 off = port << 1; |
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if (SUPERIO_PORT(port) || port & 3) |
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BUG(); |
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__raw_readsw((void __iomem *)ISAIO_BASE + off, from, len << 1); |
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} |
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EXPORT_SYMBOL(outsl); |
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EXPORT_SYMBOL(insl);
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