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454 lines
14 KiB
454 lines
14 KiB
/* |
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* arch/arm/mach-dove/common.c |
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* |
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* Core functions for Marvell Dove 88AP510 System On Chip |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_data/dma-mv_xor.h> |
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#include <linux/platform_data/usb-ehci-orion.h> |
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#include <linux/platform_device.h> |
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#include <linux/soc/dove/pmu.h> |
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#include <asm/hardware/cache-tauros2.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#include <asm/mach/time.h> |
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#include <plat/common.h> |
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#include <plat/irq.h> |
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#include <plat/time.h> |
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#include "bridge-regs.h" |
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#include "pm.h" |
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#include "common.h" |
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/* These can go away once Dove uses the mvebu-mbus DT binding */ |
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#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4 |
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#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8 |
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#define DOVE_MBUS_PCIE0_IO_TARGET 0x4 |
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#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0 |
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#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8 |
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#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8 |
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#define DOVE_MBUS_PCIE1_IO_TARGET 0x8 |
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#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0 |
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#define DOVE_MBUS_CESA_TARGET 0x3 |
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#define DOVE_MBUS_CESA_ATTR 0x1 |
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#define DOVE_MBUS_BOOTROM_TARGET 0x1 |
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#define DOVE_MBUS_BOOTROM_ATTR 0xfd |
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#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd |
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#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0 |
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/***************************************************************************** |
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* I/O Address Mapping |
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****************************************************************************/ |
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static struct map_desc __maybe_unused dove_io_desc[] __initdata = { |
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{ |
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.virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, |
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.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), |
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.length = DOVE_SB_REGS_SIZE, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, |
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.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), |
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.length = DOVE_NB_REGS_SIZE, |
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.type = MT_DEVICE, |
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}, |
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}; |
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void __init dove_map_io(void) |
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{ |
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iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); |
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} |
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/***************************************************************************** |
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* CLK tree |
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****************************************************************************/ |
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static int dove_tclk; |
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static DEFINE_SPINLOCK(gating_lock); |
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static struct clk *tclk; |
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static struct clk __init *dove_register_gate(const char *name, |
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const char *parent, u8 bit_idx) |
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{ |
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return clk_register_gate(NULL, name, parent, 0, |
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(void __iomem *)CLOCK_GATING_CONTROL, |
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bit_idx, 0, &gating_lock); |
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} |
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static void __init dove_clk_init(void) |
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{ |
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struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; |
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struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; |
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struct clk *xor0, *xor1, *ge, *gephy; |
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk); |
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usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); |
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usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); |
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sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); |
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pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); |
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pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); |
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sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); |
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sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); |
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nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); |
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camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); |
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i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); |
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i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); |
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crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); |
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ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); |
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pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); |
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xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); |
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xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); |
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gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); |
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ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); |
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orion_clkdev_add(NULL, "orion_spi.0", tclk); |
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orion_clkdev_add(NULL, "orion_spi.1", tclk); |
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orion_clkdev_add(NULL, "orion_wdt", tclk); |
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orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); |
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orion_clkdev_add(NULL, "orion-ehci.0", usb0); |
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orion_clkdev_add(NULL, "orion-ehci.1", usb1); |
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orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); |
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orion_clkdev_add(NULL, "sata_mv.0", sata); |
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orion_clkdev_add("0", "pcie", pex0); |
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orion_clkdev_add("1", "pcie", pex1); |
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orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); |
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orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); |
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orion_clkdev_add(NULL, "orion_nand", nand); |
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orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); |
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orion_clkdev_add(NULL, "mvebu-audio.0", i2s0); |
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orion_clkdev_add(NULL, "mvebu-audio.1", i2s1); |
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orion_clkdev_add(NULL, "mv_crypto", crypto); |
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orion_clkdev_add(NULL, "dove-ac97", ac97); |
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orion_clkdev_add(NULL, "dove-pdma", pdma); |
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orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); |
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orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); |
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} |
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/***************************************************************************** |
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* EHCI0 |
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****************************************************************************/ |
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void __init dove_ehci0_init(void) |
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{ |
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orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); |
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} |
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/***************************************************************************** |
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* EHCI1 |
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****************************************************************************/ |
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void __init dove_ehci1_init(void) |
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{ |
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orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); |
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} |
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/***************************************************************************** |
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* GE00 |
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****************************************************************************/ |
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void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) |
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{ |
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orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, |
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IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, |
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1600); |
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} |
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/***************************************************************************** |
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* SoC RTC |
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****************************************************************************/ |
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static void __init dove_rtc_init(void) |
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{ |
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orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); |
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} |
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/***************************************************************************** |
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* SATA |
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****************************************************************************/ |
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void __init dove_sata_init(struct mv_sata_platform_data *sata_data) |
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{ |
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orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); |
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} |
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/***************************************************************************** |
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* UART0 |
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****************************************************************************/ |
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void __init dove_uart0_init(void) |
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{ |
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orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, |
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IRQ_DOVE_UART_0, tclk); |
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} |
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/***************************************************************************** |
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* UART1 |
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****************************************************************************/ |
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void __init dove_uart1_init(void) |
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{ |
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orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, |
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IRQ_DOVE_UART_1, tclk); |
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} |
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/***************************************************************************** |
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* UART2 |
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****************************************************************************/ |
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void __init dove_uart2_init(void) |
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{ |
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orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, |
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IRQ_DOVE_UART_2, tclk); |
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} |
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/***************************************************************************** |
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* UART3 |
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****************************************************************************/ |
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void __init dove_uart3_init(void) |
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{ |
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orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, |
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IRQ_DOVE_UART_3, tclk); |
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} |
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/***************************************************************************** |
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* SPI |
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****************************************************************************/ |
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void __init dove_spi0_init(void) |
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{ |
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orion_spi_init(DOVE_SPI0_PHYS_BASE); |
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} |
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void __init dove_spi1_init(void) |
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{ |
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orion_spi_1_init(DOVE_SPI1_PHYS_BASE); |
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} |
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/***************************************************************************** |
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* I2C |
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****************************************************************************/ |
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void __init dove_i2c_init(void) |
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{ |
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orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); |
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} |
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/***************************************************************************** |
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* Time handling |
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****************************************************************************/ |
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void __init dove_init_early(void) |
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{ |
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orion_time_set_base(TIMER_VIRT_BASE); |
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mvebu_mbus_init("marvell,dove-mbus", |
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BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, |
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DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); |
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} |
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static int __init dove_find_tclk(void) |
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{ |
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return 166666667; |
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} |
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void __init dove_timer_init(void) |
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{ |
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dove_tclk = dove_find_tclk(); |
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orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, |
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IRQ_DOVE_BRIDGE, dove_tclk); |
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} |
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/***************************************************************************** |
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* XOR 0 |
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****************************************************************************/ |
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static void __init dove_xor0_init(void) |
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{ |
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orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, |
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IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); |
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} |
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/***************************************************************************** |
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* XOR 1 |
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****************************************************************************/ |
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static void __init dove_xor1_init(void) |
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{ |
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orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, |
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IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); |
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} |
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/***************************************************************************** |
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* SDIO |
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****************************************************************************/ |
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static u64 sdio_dmamask = DMA_BIT_MASK(32); |
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static struct resource dove_sdio0_resources[] = { |
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{ |
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.start = DOVE_SDIO0_PHYS_BASE, |
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.end = DOVE_SDIO0_PHYS_BASE + 0xff, |
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.flags = IORESOURCE_MEM, |
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}, { |
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.start = IRQ_DOVE_SDIO0, |
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.end = IRQ_DOVE_SDIO0, |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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static struct platform_device dove_sdio0 = { |
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.name = "sdhci-dove", |
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.id = 0, |
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.dev = { |
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.dma_mask = &sdio_dmamask, |
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.coherent_dma_mask = DMA_BIT_MASK(32), |
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}, |
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.resource = dove_sdio0_resources, |
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.num_resources = ARRAY_SIZE(dove_sdio0_resources), |
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}; |
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void __init dove_sdio0_init(void) |
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{ |
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platform_device_register(&dove_sdio0); |
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} |
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static struct resource dove_sdio1_resources[] = { |
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{ |
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.start = DOVE_SDIO1_PHYS_BASE, |
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.end = DOVE_SDIO1_PHYS_BASE + 0xff, |
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.flags = IORESOURCE_MEM, |
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}, { |
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.start = IRQ_DOVE_SDIO1, |
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.end = IRQ_DOVE_SDIO1, |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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static struct platform_device dove_sdio1 = { |
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.name = "sdhci-dove", |
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.id = 1, |
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.dev = { |
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.dma_mask = &sdio_dmamask, |
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.coherent_dma_mask = DMA_BIT_MASK(32), |
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}, |
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.resource = dove_sdio1_resources, |
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.num_resources = ARRAY_SIZE(dove_sdio1_resources), |
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}; |
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void __init dove_sdio1_init(void) |
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{ |
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platform_device_register(&dove_sdio1); |
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} |
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void __init dove_setup_cpu_wins(void) |
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{ |
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/* |
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* The PCIe windows will no longer be statically allocated |
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* here once Dove is migrated to the pci-mvebu driver. The |
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* non-PCIe windows will no longer be created here once Dove |
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* fully moves to DT. |
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*/ |
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mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET, |
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DOVE_MBUS_PCIE0_IO_ATTR, |
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DOVE_PCIE0_IO_PHYS_BASE, |
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DOVE_PCIE0_IO_SIZE, |
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DOVE_PCIE0_IO_BUS_BASE); |
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mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET, |
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DOVE_MBUS_PCIE1_IO_ATTR, |
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DOVE_PCIE1_IO_PHYS_BASE, |
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DOVE_PCIE1_IO_SIZE, |
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DOVE_PCIE1_IO_BUS_BASE); |
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mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET, |
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DOVE_MBUS_PCIE0_MEM_ATTR, |
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DOVE_PCIE0_MEM_PHYS_BASE, |
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DOVE_PCIE0_MEM_SIZE); |
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mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET, |
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DOVE_MBUS_PCIE1_MEM_ATTR, |
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DOVE_PCIE1_MEM_PHYS_BASE, |
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DOVE_PCIE1_MEM_SIZE); |
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mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET, |
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DOVE_MBUS_CESA_ATTR, |
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DOVE_CESA_PHYS_BASE, |
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DOVE_CESA_SIZE); |
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mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET, |
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DOVE_MBUS_BOOTROM_ATTR, |
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DOVE_BOOTROM_PHYS_BASE, |
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DOVE_BOOTROM_SIZE); |
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mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET, |
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DOVE_MBUS_SCRATCHPAD_ATTR, |
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DOVE_SCRATCHPAD_PHYS_BASE, |
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DOVE_SCRATCHPAD_SIZE); |
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} |
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static struct resource orion_wdt_resource[] = { |
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DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), |
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DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), |
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}; |
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static struct platform_device orion_wdt_device = { |
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.name = "orion_wdt", |
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.id = -1, |
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.num_resources = ARRAY_SIZE(orion_wdt_resource), |
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.resource = orion_wdt_resource, |
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}; |
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static void __init __maybe_unused orion_wdt_init(void) |
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{ |
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platform_device_register(&orion_wdt_device); |
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} |
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static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = { |
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{ |
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.pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK, |
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.rst_mask = PMU_SW_RST_VIDEO_MASK, |
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.iso_mask = PMU_ISO_VIDEO_MASK, |
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.name = "vpu-domain", |
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}, { |
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.pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK, |
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.rst_mask = PMU_SW_RST_GPU_MASK, |
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.iso_mask = PMU_ISO_GPU_MASK, |
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.name = "gpu-domain", |
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}, { |
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/* sentinel */ |
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}, |
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}; |
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static const struct dove_pmu_initdata pmu_data __initconst = { |
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.pmc_base = DOVE_PMU_VIRT_BASE, |
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.pmu_base = DOVE_PMU_VIRT_BASE + 0x8000, |
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.irq = IRQ_DOVE_PMU, |
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.irq_domain_start = IRQ_DOVE_PMU_START, |
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.domains = pmu_domains, |
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}; |
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void __init dove_init(void) |
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{ |
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pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", |
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(dove_tclk + 499999) / 1000000); |
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#ifdef CONFIG_CACHE_TAUROS2 |
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tauros2_init(0); |
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#endif |
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dove_setup_cpu_wins(); |
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/* Setup root of clk tree */ |
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dove_clk_init(); |
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/* internal devices that every board has */ |
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dove_init_pmu_legacy(&pmu_data); |
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dove_rtc_init(); |
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dove_xor0_init(); |
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dove_xor1_init(); |
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} |
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void dove_restart(enum reboot_mode mode, const char *cmd) |
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{ |
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/* |
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* Enable soft reset to assert RSTOUTn. |
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*/ |
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writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); |
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|
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/* |
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* Assert soft reset. |
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*/ |
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writel(SOFT_RESET, SYSTEM_SOFT_RESET); |
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while (1) |
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; |
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}
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