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152 lines
3.4 KiB
152 lines
3.4 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Actions Semi Leopard |
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* |
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* This file is based on arm realview smp platform. |
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* |
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* Copyright 2012 Actions Semi Inc. |
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* Author: Actions Semi, Inc. |
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* |
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* Copyright (c) 2017 Andreas Färber |
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*/ |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/smp.h> |
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#include <linux/soc/actions/owl-sps.h> |
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#include <asm/cacheflush.h> |
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#include <asm/smp_plat.h> |
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#include <asm/smp_scu.h> |
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#define OWL_CPU1_ADDR 0x50 |
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#define OWL_CPU1_FLAG 0x5c |
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#define OWL_CPUx_FLAG_BOOT 0x55aa |
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#define OWL_SPS_PG_CTL_PWR_CPU2 BIT(5) |
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#define OWL_SPS_PG_CTL_PWR_CPU3 BIT(6) |
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#define OWL_SPS_PG_CTL_ACK_CPU2 BIT(21) |
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#define OWL_SPS_PG_CTL_ACK_CPU3 BIT(22) |
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static void __iomem *scu_base_addr; |
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static void __iomem *sps_base_addr; |
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static void __iomem *timer_base_addr; |
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static int ncores; |
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static int s500_wakeup_secondary(unsigned int cpu) |
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{ |
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int ret; |
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if (cpu > 3) |
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return -EINVAL; |
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/* The generic PM domain driver is not available this early. */ |
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switch (cpu) { |
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case 2: |
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ret = owl_sps_set_pg(sps_base_addr, |
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OWL_SPS_PG_CTL_PWR_CPU2, |
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OWL_SPS_PG_CTL_ACK_CPU2, true); |
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if (ret) |
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return ret; |
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break; |
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case 3: |
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ret = owl_sps_set_pg(sps_base_addr, |
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OWL_SPS_PG_CTL_PWR_CPU3, |
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OWL_SPS_PG_CTL_ACK_CPU3, true); |
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if (ret) |
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return ret; |
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break; |
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} |
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/* wait for CPUx to run to WFE instruction */ |
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udelay(200); |
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writel(__pa_symbol(secondary_startup), |
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timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); |
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writel(OWL_CPUx_FLAG_BOOT, |
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timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); |
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dsb_sev(); |
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mb(); |
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return 0; |
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} |
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static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) |
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{ |
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int ret; |
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ret = s500_wakeup_secondary(cpu); |
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if (ret) |
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return ret; |
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udelay(10); |
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smp_send_reschedule(cpu); |
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writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); |
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writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); |
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return 0; |
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} |
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static void __init s500_smp_prepare_cpus(unsigned int max_cpus) |
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{ |
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struct device_node *node; |
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node = of_find_compatible_node(NULL, NULL, "actions,s500-timer"); |
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if (!node) { |
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pr_err("%s: missing timer\n", __func__); |
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return; |
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} |
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timer_base_addr = of_iomap(node, 0); |
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if (!timer_base_addr) { |
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pr_err("%s: could not map timer registers\n", __func__); |
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return; |
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} |
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node = of_find_compatible_node(NULL, NULL, "actions,s500-sps"); |
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if (!node) { |
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pr_err("%s: missing sps\n", __func__); |
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return; |
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} |
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sps_base_addr = of_iomap(node, 0); |
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if (!sps_base_addr) { |
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pr_err("%s: could not map sps registers\n", __func__); |
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return; |
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} |
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { |
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node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); |
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if (!node) { |
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pr_err("%s: missing scu\n", __func__); |
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return; |
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} |
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scu_base_addr = of_iomap(node, 0); |
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if (!scu_base_addr) { |
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pr_err("%s: could not map scu registers\n", __func__); |
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return; |
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} |
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/* |
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* While the number of cpus is gathered from dt, also get the |
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* number of cores from the scu to verify this value when |
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* booting the cores. |
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*/ |
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ncores = scu_get_core_count(scu_base_addr); |
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pr_debug("%s: ncores %d\n", __func__, ncores); |
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scu_enable(scu_base_addr); |
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} |
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} |
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static const struct smp_operations s500_smp_ops __initconst = { |
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.smp_prepare_cpus = s500_smp_prepare_cpus, |
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.smp_boot_secondary = s500_smp_boot_secondary, |
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}; |
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CPU_METHOD_OF_DECLARE(s500_smp, "actions,s500-smp", &s500_smp_ops);
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