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225 lines
5.1 KiB
225 lines
5.1 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* linux/arch/arm/kernel/dma-isa.c |
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* |
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* Copyright (C) 1999-2000 Russell King |
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* |
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* ISA DMA primitives |
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* Taken from various sources, including: |
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* linux/include/asm/dma.h: Defines for using and allocating dma channels. |
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* Written by Hennus Bergman, 1992. |
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* High DMA channel support & info by Hannu Savolainen and John Boyd, |
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* Nov. 1992. |
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* arch/arm/kernel/dma-ebsa285.c |
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* Copyright (C) 1998 Phil Blundell |
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*/ |
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#include <linux/ioport.h> |
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#include <linux/init.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/io.h> |
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#include <asm/dma.h> |
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#include <asm/mach/dma.h> |
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#define ISA_DMA_MASK 0 |
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#define ISA_DMA_MODE 1 |
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#define ISA_DMA_CLRFF 2 |
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#define ISA_DMA_PGHI 3 |
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#define ISA_DMA_PGLO 4 |
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#define ISA_DMA_ADDR 5 |
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#define ISA_DMA_COUNT 6 |
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static unsigned int isa_dma_port[8][7] = { |
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/* MASK MODE CLRFF PAGE_HI PAGE_LO ADDR COUNT */ |
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{ 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 }, |
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{ 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 }, |
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{ 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 }, |
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{ 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 }, |
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{ 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 }, |
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{ 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 }, |
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{ 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca }, |
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{ 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce } |
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}; |
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static int isa_get_dma_residue(unsigned int chan, dma_t *dma) |
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{ |
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unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT]; |
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int count; |
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count = 1 + inb(io_port); |
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count |= inb(io_port) << 8; |
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return chan < 4 ? count : (count << 1); |
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} |
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static struct device isa_dma_dev = { |
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.init_name = "fallback device", |
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.coherent_dma_mask = ~(dma_addr_t)0, |
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.dma_mask = &isa_dma_dev.coherent_dma_mask, |
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}; |
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static void isa_enable_dma(unsigned int chan, dma_t *dma) |
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{ |
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if (dma->invalid) { |
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unsigned long address, length; |
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unsigned int mode; |
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enum dma_data_direction direction; |
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mode = (chan & 3) | dma->dma_mode; |
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switch (dma->dma_mode & DMA_MODE_MASK) { |
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case DMA_MODE_READ: |
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direction = DMA_FROM_DEVICE; |
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break; |
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case DMA_MODE_WRITE: |
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direction = DMA_TO_DEVICE; |
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break; |
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case DMA_MODE_CASCADE: |
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direction = DMA_BIDIRECTIONAL; |
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break; |
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default: |
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direction = DMA_NONE; |
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break; |
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} |
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if (!dma->sg) { |
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/* |
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* Cope with ISA-style drivers which expect cache |
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* coherence. |
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*/ |
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dma->sg = &dma->buf; |
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dma->sgcount = 1; |
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dma->buf.length = dma->count; |
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dma->buf.dma_address = dma_map_single(&isa_dma_dev, |
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dma->addr, dma->count, |
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direction); |
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} |
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address = dma->buf.dma_address; |
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length = dma->buf.length - 1; |
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outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]); |
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outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]); |
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if (chan >= 4) { |
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address >>= 1; |
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length >>= 1; |
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} |
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outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]); |
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outb(address, isa_dma_port[chan][ISA_DMA_ADDR]); |
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outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]); |
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outb(length, isa_dma_port[chan][ISA_DMA_COUNT]); |
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outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]); |
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outb(mode, isa_dma_port[chan][ISA_DMA_MODE]); |
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dma->invalid = 0; |
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} |
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outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]); |
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} |
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static void isa_disable_dma(unsigned int chan, dma_t *dma) |
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{ |
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outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]); |
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} |
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static struct dma_ops isa_dma_ops = { |
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.type = "ISA", |
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.enable = isa_enable_dma, |
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.disable = isa_disable_dma, |
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.residue = isa_get_dma_residue, |
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}; |
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static struct resource dma_resources[] = { { |
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.name = "dma1", |
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.start = 0x0000, |
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.end = 0x000f |
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}, { |
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.name = "dma low page", |
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.start = 0x0080, |
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.end = 0x008f |
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}, { |
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.name = "dma2", |
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.start = 0x00c0, |
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.end = 0x00df |
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}, { |
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.name = "dma high page", |
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.start = 0x0480, |
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.end = 0x048f |
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} }; |
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static dma_t isa_dma[8]; |
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/* |
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* ISA DMA always starts at channel 0 |
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*/ |
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void __init isa_init_dma(void) |
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{ |
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/* |
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* Try to autodetect presence of an ISA DMA controller. |
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* We do some minimal initialisation, and check that |
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* channel 0's DMA address registers are writeable. |
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*/ |
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outb(0xff, 0x0d); |
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outb(0xff, 0xda); |
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/* |
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* Write high and low address, and then read them back |
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* in the same order. |
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*/ |
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outb(0x55, 0x00); |
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outb(0xaa, 0x00); |
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if (inb(0) == 0x55 && inb(0) == 0xaa) { |
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unsigned int chan, i; |
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for (chan = 0; chan < 8; chan++) { |
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isa_dma[chan].d_ops = &isa_dma_ops; |
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isa_disable_dma(chan, NULL); |
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} |
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outb(0x40, 0x0b); |
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outb(0x41, 0x0b); |
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outb(0x42, 0x0b); |
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outb(0x43, 0x0b); |
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outb(0xc0, 0xd6); |
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outb(0x41, 0xd6); |
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outb(0x42, 0xd6); |
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outb(0x43, 0xd6); |
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outb(0, 0xd4); |
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outb(0x10, 0x08); |
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outb(0x10, 0xd0); |
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/* |
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* Is this correct? According to my documentation, it |
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* doesn't appear to be. It should be: |
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* outb(0x3f, 0x40b); outb(0x3f, 0x4d6); |
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*/ |
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outb(0x30, 0x40b); |
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outb(0x31, 0x40b); |
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outb(0x32, 0x40b); |
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outb(0x33, 0x40b); |
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outb(0x31, 0x4d6); |
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outb(0x32, 0x4d6); |
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outb(0x33, 0x4d6); |
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for (i = 0; i < ARRAY_SIZE(dma_resources); i++) |
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request_resource(&ioport_resource, dma_resources + i); |
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for (chan = 0; chan < 8; chan++) { |
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int ret = isa_dma_add(chan, &isa_dma[chan]); |
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if (ret) |
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pr_err("ISADMA%u: unable to register: %d\n", |
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chan, ret); |
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} |
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request_dma(DMA_ISA_CASCADE, "cascade"); |
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} |
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}
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