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173 lines
4.4 KiB
173 lines
4.4 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* ARC CPU startup Code |
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* |
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
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* |
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* Vineetg: Dec 2007 |
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* -Check if we are running on Simulator or on real hardware |
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* to skip certain things during boot on simulator |
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*/ |
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#include <linux/linkage.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/entry.h> |
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#include <asm/arcregs.h> |
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#include <asm/cache.h> |
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#include <asm/dsp-impl.h> |
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#include <asm/irqflags.h> |
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.macro CPU_EARLY_SETUP |
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; Setting up Vectror Table (in case exception happens in early boot |
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sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] |
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; Disable I-cache/D-cache if kernel so configured |
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lr r5, [ARC_REG_IC_BCR] |
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breq r5, 0, 1f ; I$ doesn't exist |
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lr r5, [ARC_REG_IC_CTRL] |
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#ifdef CONFIG_ARC_HAS_ICACHE |
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bclr r5, r5, 0 ; 0 - Enable, 1 is Disable |
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#else |
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bset r5, r5, 0 ; I$ exists, but is not used |
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#endif |
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sr r5, [ARC_REG_IC_CTRL] |
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1: |
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lr r5, [ARC_REG_DC_BCR] |
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breq r5, 0, 1f ; D$ doesn't exist |
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lr r5, [ARC_REG_DC_CTRL] |
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bclr r5, r5, 6 ; Invalidate (discard w/o wback) |
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#ifdef CONFIG_ARC_HAS_DCACHE |
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bclr r5, r5, 0 ; Enable (+Inv) |
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#else |
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bset r5, r5, 0 ; Disable (+Inv) |
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#endif |
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sr r5, [ARC_REG_DC_CTRL] |
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1: |
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#ifdef CONFIG_ISA_ARCV2 |
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; Unaligned access is disabled at reset, so re-enable early as |
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; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access |
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; by default |
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lr r5, [status32] |
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#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS |
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bset r5, r5, STATUS_AD_BIT |
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#else |
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; Although disabled at reset, bootloader might have enabled it |
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bclr r5, r5, STATUS_AD_BIT |
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#endif |
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kflag r5 |
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#ifdef CONFIG_ARC_LPB_DISABLE |
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lr r5, [ARC_REG_LPB_BUILD] |
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breq r5, 0, 1f ; LPB doesn't exist |
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mov r5, 1 |
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sr r5, [ARC_REG_LPB_CTRL] |
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1: |
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#endif /* CONFIG_ARC_LPB_DISABLE */ |
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/* On HSDK, CCMs need to remapped super early */ |
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#ifdef CONFIG_ARC_SOC_HSDK |
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mov r6, 0x60000000 |
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lr r5, [ARC_REG_ICCM_BUILD] |
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breq r5, 0, 1f |
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sr r6, [ARC_REG_AUX_ICCM] |
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1: |
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lr r5, [ARC_REG_DCCM_BUILD] |
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breq r5, 0, 2f |
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sr r6, [ARC_REG_AUX_DCCM] |
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2: |
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#endif /* CONFIG_ARC_SOC_HSDK */ |
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#endif /* CONFIG_ISA_ARCV2 */ |
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; Config DSP_CTRL properly, so kernel may use integer multiply, |
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; multiply-accumulate, and divide operations |
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DSP_EARLY_INIT |
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.endm |
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.section .init.text, "ax",@progbits |
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;---------------------------------------------------------------- |
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; Default Reset Handler (jumped into from Reset vector) |
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; - Don't clobber r0,r1,r2 as they might have u-boot provided args |
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; - Platforms can override this weak version if needed |
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;---------------------------------------------------------------- |
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WEAK(res_service) |
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j stext |
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END(res_service) |
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;---------------------------------------------------------------- |
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; Kernel Entry point |
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;---------------------------------------------------------------- |
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ENTRY(stext) |
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CPU_EARLY_SETUP |
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#ifdef CONFIG_SMP |
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GET_CPU_ID r5 |
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cmp r5, 0 |
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mov.nz r0, r5 |
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bz .Lmaster_proceed |
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; Non-Masters wait for Master to boot enough and bring them up |
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; when they resume, tail-call to entry point |
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mov blink, @first_lines_of_secondary |
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j arc_platform_smp_wait_to_boot |
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.Lmaster_proceed: |
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#endif |
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; Clear BSS before updating any globals |
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; XXX: use ZOL here |
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mov r5, __bss_start |
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sub r6, __bss_stop, r5 |
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lsr.f lp_count, r6, 2 |
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lpnz 1f |
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st.ab 0, [r5, 4] |
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1: |
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; Uboot - kernel ABI |
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; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2 |
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; r1 = magic number (always zero as of now) |
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; r2 = pointer to uboot provided cmdline or external DTB in mem |
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; These are handled later in handle_uboot_args() |
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st r0, [@uboot_tag] |
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st r1, [@uboot_magic] |
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st r2, [@uboot_arg] |
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; setup "current" tsk and optionally cache it in dedicated r25 |
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mov r9, @init_task |
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SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch |
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; setup stack (fp, sp) |
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mov fp, 0 |
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; tsk->thread_info is really a PAGE, whose bottom hoists stack |
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GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output) |
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j start_kernel ; "C" entry point |
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END(stext) |
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#ifdef CONFIG_SMP |
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;---------------------------------------------------------------- |
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; First lines of code run by secondary before jumping to 'C' |
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;---------------------------------------------------------------- |
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.section .text, "ax",@progbits |
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ENTRY(first_lines_of_secondary) |
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; setup per-cpu idle task as "current" on this CPU |
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ld r0, [@secondary_idle_tsk] |
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SET_CURR_TASK_ON_CPU r0, r1 |
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; setup stack (fp, sp) |
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mov fp, 0 |
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; set it's stack base to tsk->thread_info bottom |
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GET_TSK_STACK_BASE r0, sp |
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j start_kernel_secondary |
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END(first_lines_of_secondary) |
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#endif
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