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535 lines
14 KiB
535 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* several functions that help interpret ARC instructions |
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* used for unaligned accesses, kprobes and kgdb |
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* |
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
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*/ |
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#include <linux/types.h> |
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#include <linux/kprobes.h> |
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#include <linux/slab.h> |
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#include <linux/uaccess.h> |
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#include <asm/disasm.h> |
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#if defined(CONFIG_KGDB) || defined(CONFIG_ARC_EMUL_UNALIGNED) || \ |
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defined(CONFIG_KPROBES) |
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/* disasm_instr: Analyses instruction at addr, stores |
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* findings in *state |
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*/ |
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void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state, |
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int userspace, struct pt_regs *regs, struct callee_regs *cregs) |
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{ |
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int fieldA = 0; |
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int fieldC = 0, fieldCisReg = 0; |
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uint16_t word1 = 0, word0 = 0; |
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int subopcode, is_linked, op_format; |
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uint16_t *ins_ptr; |
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uint16_t ins_buf[4]; |
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int bytes_not_copied = 0; |
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memset(state, 0, sizeof(struct disasm_state)); |
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|
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/* This fetches the upper part of the 32 bit instruction |
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* in both the cases of Little Endian or Big Endian configurations. */ |
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if (userspace) { |
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bytes_not_copied = copy_from_user(ins_buf, |
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(const void __user *) addr, 8); |
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if (bytes_not_copied > 6) |
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goto fault; |
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ins_ptr = ins_buf; |
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} else { |
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ins_ptr = (uint16_t *) addr; |
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} |
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word1 = *((uint16_t *)addr); |
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state->major_opcode = (word1 >> 11) & 0x1F; |
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/* Check if the instruction is 32 bit or 16 bit instruction */ |
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if (state->major_opcode < 0x0B) { |
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if (bytes_not_copied > 4) |
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goto fault; |
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state->instr_len = 4; |
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word0 = *((uint16_t *)(addr+2)); |
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state->words[0] = (word1 << 16) | word0; |
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} else { |
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state->instr_len = 2; |
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state->words[0] = word1; |
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} |
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|
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/* Read the second word in case of limm */ |
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word1 = *((uint16_t *)(addr + state->instr_len)); |
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word0 = *((uint16_t *)(addr + state->instr_len + 2)); |
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state->words[1] = (word1 << 16) | word0; |
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switch (state->major_opcode) { |
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case op_Bcc: |
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state->is_branch = 1; |
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/* unconditional branch s25, conditional branch s21 */ |
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fieldA = (IS_BIT(state->words[0], 16)) ? |
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FIELD_s25(state->words[0]) : |
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FIELD_s21(state->words[0]); |
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state->delay_slot = IS_BIT(state->words[0], 5); |
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state->target = fieldA + (addr & ~0x3); |
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state->flow = direct_jump; |
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break; |
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case op_BLcc: |
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if (IS_BIT(state->words[0], 16)) { |
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/* Branch and Link*/ |
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/* unconditional branch s25, conditional branch s21 */ |
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fieldA = (IS_BIT(state->words[0], 17)) ? |
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(FIELD_s25(state->words[0]) & ~0x3) : |
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FIELD_s21(state->words[0]); |
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state->flow = direct_call; |
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} else { |
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/*Branch On Compare */ |
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fieldA = FIELD_s9(state->words[0]) & ~0x3; |
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state->flow = direct_jump; |
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} |
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state->delay_slot = IS_BIT(state->words[0], 5); |
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state->target = fieldA + (addr & ~0x3); |
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state->is_branch = 1; |
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break; |
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case op_LD: /* LD<zz> a,[b,s9] */ |
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state->write = 0; |
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state->di = BITS(state->words[0], 11, 11); |
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if (state->di) |
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break; |
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state->x = BITS(state->words[0], 6, 6); |
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state->zz = BITS(state->words[0], 7, 8); |
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state->aa = BITS(state->words[0], 9, 10); |
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state->wb_reg = FIELD_B(state->words[0]); |
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if (state->wb_reg == REG_LIMM) { |
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state->instr_len += 4; |
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state->aa = 0; |
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state->src1 = state->words[1]; |
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} else { |
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state->src1 = get_reg(state->wb_reg, regs, cregs); |
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} |
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state->src2 = FIELD_s9(state->words[0]); |
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state->dest = FIELD_A(state->words[0]); |
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state->pref = (state->dest == REG_LIMM); |
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break; |
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case op_ST: |
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state->write = 1; |
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state->di = BITS(state->words[0], 5, 5); |
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if (state->di) |
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break; |
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state->aa = BITS(state->words[0], 3, 4); |
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state->zz = BITS(state->words[0], 1, 2); |
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state->src1 = FIELD_C(state->words[0]); |
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if (state->src1 == REG_LIMM) { |
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state->instr_len += 4; |
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state->src1 = state->words[1]; |
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} else { |
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state->src1 = get_reg(state->src1, regs, cregs); |
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} |
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state->wb_reg = FIELD_B(state->words[0]); |
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if (state->wb_reg == REG_LIMM) { |
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state->aa = 0; |
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state->instr_len += 4; |
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state->src2 = state->words[1]; |
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} else { |
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state->src2 = get_reg(state->wb_reg, regs, cregs); |
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} |
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state->src3 = FIELD_s9(state->words[0]); |
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break; |
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case op_MAJOR_4: |
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subopcode = MINOR_OPCODE(state->words[0]); |
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switch (subopcode) { |
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case 32: /* Jcc */ |
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case 33: /* Jcc.D */ |
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case 34: /* JLcc */ |
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case 35: /* JLcc.D */ |
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is_linked = 0; |
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if (subopcode == 33 || subopcode == 35) |
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state->delay_slot = 1; |
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if (subopcode == 34 || subopcode == 35) |
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is_linked = 1; |
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fieldCisReg = 0; |
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op_format = BITS(state->words[0], 22, 23); |
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if (op_format == 0 || ((op_format == 3) && |
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(!IS_BIT(state->words[0], 5)))) { |
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fieldC = FIELD_C(state->words[0]); |
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if (fieldC == REG_LIMM) { |
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fieldC = state->words[1]; |
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state->instr_len += 4; |
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} else { |
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fieldCisReg = 1; |
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} |
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} else if (op_format == 1 || ((op_format == 3) |
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&& (IS_BIT(state->words[0], 5)))) { |
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fieldC = FIELD_C(state->words[0]); |
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} else { |
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/* op_format == 2 */ |
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fieldC = FIELD_s12(state->words[0]); |
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} |
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if (!fieldCisReg) { |
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state->target = fieldC; |
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state->flow = is_linked ? |
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direct_call : direct_jump; |
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} else { |
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state->target = get_reg(fieldC, regs, cregs); |
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state->flow = is_linked ? |
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indirect_call : indirect_jump; |
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} |
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state->is_branch = 1; |
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break; |
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case 40: /* LPcc */ |
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if (BITS(state->words[0], 22, 23) == 3) { |
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/* Conditional LPcc u7 */ |
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fieldC = FIELD_C(state->words[0]); |
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fieldC = fieldC << 1; |
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fieldC += (addr & ~0x03); |
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state->is_branch = 1; |
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state->flow = direct_jump; |
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state->target = fieldC; |
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} |
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/* For Unconditional lp, next pc is the fall through |
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* which is updated */ |
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break; |
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case 48 ... 55: /* LD a,[b,c] */ |
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state->di = BITS(state->words[0], 15, 15); |
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if (state->di) |
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break; |
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state->x = BITS(state->words[0], 16, 16); |
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state->zz = BITS(state->words[0], 17, 18); |
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state->aa = BITS(state->words[0], 22, 23); |
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state->wb_reg = FIELD_B(state->words[0]); |
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if (state->wb_reg == REG_LIMM) { |
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state->instr_len += 4; |
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state->src1 = state->words[1]; |
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} else { |
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state->src1 = get_reg(state->wb_reg, regs, |
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cregs); |
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} |
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state->src2 = FIELD_C(state->words[0]); |
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if (state->src2 == REG_LIMM) { |
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state->instr_len += 4; |
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state->src2 = state->words[1]; |
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} else { |
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state->src2 = get_reg(state->src2, regs, |
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cregs); |
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} |
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state->dest = FIELD_A(state->words[0]); |
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if (state->dest == REG_LIMM) |
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state->pref = 1; |
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break; |
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case 10: /* MOV */ |
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/* still need to check for limm to extract instr len */ |
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/* MOV is special case because it only takes 2 args */ |
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switch (BITS(state->words[0], 22, 23)) { |
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case 0: /* OP a,b,c */ |
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if (FIELD_C(state->words[0]) == REG_LIMM) |
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state->instr_len += 4; |
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break; |
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case 1: /* OP a,b,u6 */ |
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break; |
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case 2: /* OP b,b,s12 */ |
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break; |
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case 3: /* OP.cc b,b,c/u6 */ |
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if ((!IS_BIT(state->words[0], 5)) && |
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(FIELD_C(state->words[0]) == REG_LIMM)) |
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state->instr_len += 4; |
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break; |
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} |
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break; |
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default: |
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/* Not a Load, Jump or Loop instruction */ |
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/* still need to check for limm to extract instr len */ |
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switch (BITS(state->words[0], 22, 23)) { |
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case 0: /* OP a,b,c */ |
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if ((FIELD_B(state->words[0]) == REG_LIMM) || |
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(FIELD_C(state->words[0]) == REG_LIMM)) |
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state->instr_len += 4; |
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break; |
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case 1: /* OP a,b,u6 */ |
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break; |
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case 2: /* OP b,b,s12 */ |
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break; |
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case 3: /* OP.cc b,b,c/u6 */ |
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if ((!IS_BIT(state->words[0], 5)) && |
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((FIELD_B(state->words[0]) == REG_LIMM) || |
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(FIELD_C(state->words[0]) == REG_LIMM))) |
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state->instr_len += 4; |
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break; |
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} |
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break; |
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} |
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break; |
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/* 16 Bit Instructions */ |
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case op_LD_ADD: /* LD_S|LDB_S|LDW_S a,[b,c] */ |
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state->zz = BITS(state->words[0], 3, 4); |
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state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); |
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state->src2 = get_reg(FIELD_S_C(state->words[0]), regs, cregs); |
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state->dest = FIELD_S_A(state->words[0]); |
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break; |
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case op_ADD_MOV_CMP: |
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/* check for limm, ignore mov_s h,b (== mov_s 0,b) */ |
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if ((BITS(state->words[0], 3, 4) < 3) && |
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(FIELD_S_H(state->words[0]) == REG_LIMM)) |
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state->instr_len += 4; |
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break; |
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case op_S: |
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subopcode = BITS(state->words[0], 5, 7); |
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switch (subopcode) { |
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case 0: /* j_s */ |
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case 1: /* j_s.d */ |
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case 2: /* jl_s */ |
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case 3: /* jl_s.d */ |
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state->target = get_reg(FIELD_S_B(state->words[0]), |
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regs, cregs); |
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state->delay_slot = subopcode & 1; |
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state->flow = (subopcode >= 2) ? |
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direct_call : indirect_jump; |
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break; |
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case 7: |
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switch (BITS(state->words[0], 8, 10)) { |
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case 4: /* jeq_s [blink] */ |
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case 5: /* jne_s [blink] */ |
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case 6: /* j_s [blink] */ |
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case 7: /* j_s.d [blink] */ |
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state->delay_slot = (subopcode == 7); |
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state->flow = indirect_jump; |
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state->target = get_reg(31, regs, cregs); |
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default: |
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break; |
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} |
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default: |
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break; |
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} |
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break; |
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case op_LD_S: /* LD_S c, [b, u7] */ |
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state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); |
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state->src2 = FIELD_S_u7(state->words[0]); |
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state->dest = FIELD_S_C(state->words[0]); |
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break; |
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case op_LDB_S: |
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case op_STB_S: |
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/* no further handling required as byte accesses should not |
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* cause an unaligned access exception */ |
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state->zz = 1; |
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break; |
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case op_LDWX_S: /* LDWX_S c, [b, u6] */ |
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state->x = 1; |
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fallthrough; |
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case op_LDW_S: /* LDW_S c, [b, u6] */ |
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state->zz = 2; |
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state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); |
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state->src2 = FIELD_S_u6(state->words[0]); |
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state->dest = FIELD_S_C(state->words[0]); |
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break; |
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case op_ST_S: /* ST_S c, [b, u7] */ |
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state->write = 1; |
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state->src1 = get_reg(FIELD_S_C(state->words[0]), regs, cregs); |
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state->src2 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); |
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state->src3 = FIELD_S_u7(state->words[0]); |
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break; |
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case op_STW_S: /* STW_S c,[b,u6] */ |
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state->write = 1; |
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state->zz = 2; |
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state->src1 = get_reg(FIELD_S_C(state->words[0]), regs, cregs); |
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state->src2 = get_reg(FIELD_S_B(state->words[0]), regs, cregs); |
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state->src3 = FIELD_S_u6(state->words[0]); |
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break; |
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case op_SP: /* LD_S|LDB_S b,[sp,u7], ST_S|STB_S b,[sp,u7] */ |
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/* note: we are ignoring possibility of: |
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* ADD_S, SUB_S, PUSH_S, POP_S as these should not |
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* cause unaliged exception anyway */ |
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state->write = BITS(state->words[0], 6, 6); |
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state->zz = BITS(state->words[0], 5, 5); |
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if (state->zz) |
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break; /* byte accesses should not come here */ |
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if (!state->write) { |
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state->src1 = get_reg(28, regs, cregs); |
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state->src2 = FIELD_S_u7(state->words[0]); |
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state->dest = FIELD_S_B(state->words[0]); |
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} else { |
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state->src1 = get_reg(FIELD_S_B(state->words[0]), regs, |
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cregs); |
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state->src2 = get_reg(28, regs, cregs); |
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state->src3 = FIELD_S_u7(state->words[0]); |
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} |
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break; |
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case op_GP: /* LD_S|LDB_S|LDW_S r0,[gp,s11/s9/s10] */ |
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/* note: ADD_S r0, gp, s11 is ignored */ |
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state->zz = BITS(state->words[0], 9, 10); |
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state->src1 = get_reg(26, regs, cregs); |
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state->src2 = state->zz ? FIELD_S_s10(state->words[0]) : |
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FIELD_S_s11(state->words[0]); |
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state->dest = 0; |
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break; |
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case op_Pcl: /* LD_S b,[pcl,u10] */ |
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state->src1 = regs->ret & ~3; |
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state->src2 = FIELD_S_u10(state->words[0]); |
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state->dest = FIELD_S_B(state->words[0]); |
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break; |
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case op_BR_S: |
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state->target = FIELD_S_s8(state->words[0]) + (addr & ~0x03); |
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state->flow = direct_jump; |
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state->is_branch = 1; |
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break; |
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case op_B_S: |
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fieldA = (BITS(state->words[0], 9, 10) == 3) ? |
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FIELD_S_s7(state->words[0]) : |
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FIELD_S_s10(state->words[0]); |
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state->target = fieldA + (addr & ~0x03); |
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state->flow = direct_jump; |
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state->is_branch = 1; |
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break; |
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case op_BL_S: |
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state->target = FIELD_S_s13(state->words[0]) + (addr & ~0x03); |
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state->flow = direct_call; |
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state->is_branch = 1; |
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break; |
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default: |
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break; |
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} |
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if (bytes_not_copied <= (8 - state->instr_len)) |
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return; |
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fault: state->fault = 1; |
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} |
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long __kprobes get_reg(int reg, struct pt_regs *regs, |
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struct callee_regs *cregs) |
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{ |
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long *p; |
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if (reg <= 12) { |
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p = ®s->r0; |
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return p[-reg]; |
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} |
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if (cregs && (reg <= 25)) { |
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p = &cregs->r13; |
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return p[13-reg]; |
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} |
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if (reg == 26) |
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return regs->r26; |
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if (reg == 27) |
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return regs->fp; |
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if (reg == 28) |
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return regs->sp; |
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if (reg == 31) |
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return regs->blink; |
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|
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return 0; |
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} |
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void __kprobes set_reg(int reg, long val, struct pt_regs *regs, |
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struct callee_regs *cregs) |
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{ |
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long *p; |
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|
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switch (reg) { |
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case 0 ... 12: |
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p = ®s->r0; |
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p[-reg] = val; |
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break; |
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case 13 ... 25: |
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if (cregs) { |
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p = &cregs->r13; |
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p[13-reg] = val; |
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} |
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break; |
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case 26: |
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regs->r26 = val; |
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break; |
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case 27: |
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regs->fp = val; |
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break; |
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case 28: |
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regs->sp = val; |
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break; |
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case 31: |
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regs->blink = val; |
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break; |
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default: |
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break; |
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} |
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} |
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|
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/* |
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* Disassembles the insn at @pc and sets @next_pc to next PC (which could be |
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* @pc +2/4/6 (ARCompact ISA allows free intermixing of 16/32 bit insns). |
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* |
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* If @pc is a branch |
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* -@tgt_if_br is set to branch target. |
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* -If branch has delay slot, @next_pc updated with actual next PC. |
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*/ |
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int __kprobes disasm_next_pc(unsigned long pc, struct pt_regs *regs, |
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struct callee_regs *cregs, |
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unsigned long *next_pc, unsigned long *tgt_if_br) |
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{ |
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struct disasm_state instr; |
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|
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memset(&instr, 0, sizeof(struct disasm_state)); |
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disasm_instr(pc, &instr, 0, regs, cregs); |
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|
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*next_pc = pc + instr.instr_len; |
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|
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/* Instruction with possible two targets branch, jump and loop */ |
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if (instr.is_branch) |
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*tgt_if_br = instr.target; |
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|
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/* For the instructions with delay slots, the fall through is the |
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* instruction following the instruction in delay slot. |
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*/ |
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if (instr.delay_slot) { |
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struct disasm_state instr_d; |
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|
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disasm_instr(*next_pc, &instr_d, 0, regs, cregs); |
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|
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*next_pc += instr_d.instr_len; |
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} |
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|
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/* Zero Overhead Loop - end of the loop */ |
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if (!(regs->status32 & STATUS32_L) && (*next_pc == regs->lp_end) |
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&& (regs->lp_count > 1)) { |
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*next_pc = regs->lp_start; |
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} |
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|
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return instr.is_branch; |
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} |
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|
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#endif /* CONFIG_KGDB || CONFIG_ARC_EMUL_UNALIGNED || CONFIG_KPROBES */
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