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935 lines
24 KiB
935 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC |
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* |
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* Author: Florian Meier <[email protected]> |
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* Copyright 2013 |
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* |
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* Based on |
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* Raspberry Pi PCM I2S ALSA Driver |
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* Copyright (c) by Phil Poole 2013 |
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* |
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* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor |
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* Vladimir Barinov, <[email protected]> |
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* Copyright (C) 2007 MontaVista Software, Inc., <[email protected]> |
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* |
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* OMAP ALSA SoC DAI driver using McBSP port |
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* Copyright (C) 2008 Nokia Corporation |
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* Contact: Jarkko Nikula <[email protected]> |
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* Peter Ujfalusi <[email protected]> |
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* |
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* Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver |
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* Author: Timur Tabi <[email protected]> |
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* Copyright 2007-2010 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include <sound/core.h> |
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#include <sound/dmaengine_pcm.h> |
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#include <sound/initval.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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/* I2S registers */ |
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#define BCM2835_I2S_CS_A_REG 0x00 |
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#define BCM2835_I2S_FIFO_A_REG 0x04 |
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#define BCM2835_I2S_MODE_A_REG 0x08 |
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#define BCM2835_I2S_RXC_A_REG 0x0c |
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#define BCM2835_I2S_TXC_A_REG 0x10 |
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#define BCM2835_I2S_DREQ_A_REG 0x14 |
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#define BCM2835_I2S_INTEN_A_REG 0x18 |
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#define BCM2835_I2S_INTSTC_A_REG 0x1c |
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#define BCM2835_I2S_GRAY_REG 0x20 |
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|
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/* I2S register settings */ |
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#define BCM2835_I2S_STBY BIT(25) |
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#define BCM2835_I2S_SYNC BIT(24) |
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#define BCM2835_I2S_RXSEX BIT(23) |
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#define BCM2835_I2S_RXF BIT(22) |
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#define BCM2835_I2S_TXE BIT(21) |
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#define BCM2835_I2S_RXD BIT(20) |
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#define BCM2835_I2S_TXD BIT(19) |
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#define BCM2835_I2S_RXR BIT(18) |
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#define BCM2835_I2S_TXW BIT(17) |
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#define BCM2835_I2S_CS_RXERR BIT(16) |
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#define BCM2835_I2S_CS_TXERR BIT(15) |
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#define BCM2835_I2S_RXSYNC BIT(14) |
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#define BCM2835_I2S_TXSYNC BIT(13) |
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#define BCM2835_I2S_DMAEN BIT(9) |
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#define BCM2835_I2S_RXTHR(v) ((v) << 7) |
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#define BCM2835_I2S_TXTHR(v) ((v) << 5) |
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#define BCM2835_I2S_RXCLR BIT(4) |
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#define BCM2835_I2S_TXCLR BIT(3) |
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#define BCM2835_I2S_TXON BIT(2) |
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#define BCM2835_I2S_RXON BIT(1) |
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#define BCM2835_I2S_EN (1) |
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#define BCM2835_I2S_CLKDIS BIT(28) |
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#define BCM2835_I2S_PDMN BIT(27) |
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#define BCM2835_I2S_PDME BIT(26) |
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#define BCM2835_I2S_FRXP BIT(25) |
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#define BCM2835_I2S_FTXP BIT(24) |
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#define BCM2835_I2S_CLKM BIT(23) |
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#define BCM2835_I2S_CLKI BIT(22) |
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#define BCM2835_I2S_FSM BIT(21) |
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#define BCM2835_I2S_FSI BIT(20) |
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#define BCM2835_I2S_FLEN(v) ((v) << 10) |
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#define BCM2835_I2S_FSLEN(v) (v) |
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#define BCM2835_I2S_CHWEX BIT(15) |
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#define BCM2835_I2S_CHEN BIT(14) |
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#define BCM2835_I2S_CHPOS(v) ((v) << 4) |
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#define BCM2835_I2S_CHWID(v) (v) |
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#define BCM2835_I2S_CH1(v) ((v) << 16) |
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#define BCM2835_I2S_CH2(v) (v) |
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#define BCM2835_I2S_CH1_POS(v) BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v)) |
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#define BCM2835_I2S_CH2_POS(v) BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v)) |
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#define BCM2835_I2S_TX_PANIC(v) ((v) << 24) |
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#define BCM2835_I2S_RX_PANIC(v) ((v) << 16) |
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#define BCM2835_I2S_TX(v) ((v) << 8) |
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#define BCM2835_I2S_RX(v) (v) |
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#define BCM2835_I2S_INT_RXERR BIT(3) |
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#define BCM2835_I2S_INT_TXERR BIT(2) |
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#define BCM2835_I2S_INT_RXR BIT(1) |
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#define BCM2835_I2S_INT_TXW BIT(0) |
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/* Frame length register is 10 bit, maximum length 1024 */ |
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#define BCM2835_I2S_MAX_FRAME_LENGTH 1024 |
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/* General device struct */ |
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struct bcm2835_i2s_dev { |
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struct device *dev; |
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struct snd_dmaengine_dai_dma_data dma_data[2]; |
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unsigned int fmt; |
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unsigned int tdm_slots; |
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unsigned int rx_mask; |
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unsigned int tx_mask; |
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unsigned int slot_width; |
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unsigned int frame_length; |
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struct regmap *i2s_regmap; |
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struct clk *clk; |
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bool clk_prepared; |
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int clk_rate; |
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}; |
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static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev) |
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{ |
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unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; |
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if (dev->clk_prepared) |
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return; |
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switch (master) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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case SND_SOC_DAIFMT_CBS_CFM: |
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clk_prepare_enable(dev->clk); |
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dev->clk_prepared = true; |
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break; |
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default: |
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break; |
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} |
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} |
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static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev) |
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{ |
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if (dev->clk_prepared) |
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clk_disable_unprepare(dev->clk); |
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dev->clk_prepared = false; |
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} |
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static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev, |
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bool tx, bool rx) |
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{ |
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int timeout = 1000; |
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uint32_t syncval; |
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uint32_t csreg; |
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uint32_t i2s_active_state; |
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bool clk_was_prepared; |
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uint32_t off; |
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uint32_t clr; |
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off = tx ? BCM2835_I2S_TXON : 0; |
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off |= rx ? BCM2835_I2S_RXON : 0; |
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clr = tx ? BCM2835_I2S_TXCLR : 0; |
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clr |= rx ? BCM2835_I2S_RXCLR : 0; |
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/* Backup the current state */ |
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regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg); |
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i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON); |
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/* Start clock if not running */ |
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clk_was_prepared = dev->clk_prepared; |
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if (!clk_was_prepared) |
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bcm2835_i2s_start_clock(dev); |
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/* Stop I2S module */ |
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regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0); |
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/* |
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* Clear the FIFOs |
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* Requires at least 2 PCM clock cycles to take effect |
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*/ |
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regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr); |
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/* Wait for 2 PCM clock cycles */ |
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/* |
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* Toggle the SYNC flag. After 2 PCM clock cycles it can be read back |
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* FIXME: This does not seem to work for slave mode! |
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*/ |
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regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval); |
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syncval &= BCM2835_I2S_SYNC; |
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regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, |
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BCM2835_I2S_SYNC, ~syncval); |
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/* Wait for the SYNC flag changing it's state */ |
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while (--timeout) { |
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regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg); |
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if ((csreg & BCM2835_I2S_SYNC) != syncval) |
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break; |
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} |
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if (!timeout) |
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dev_err(dev->dev, "I2S SYNC error!\n"); |
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/* Stop clock if it was not running before */ |
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if (!clk_was_prepared) |
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bcm2835_i2s_stop_clock(dev); |
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/* Restore I2S state */ |
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regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, |
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BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state); |
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} |
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static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai, |
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unsigned int fmt) |
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{ |
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struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
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dev->fmt = fmt; |
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return 0; |
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} |
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static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, |
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unsigned int ratio) |
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{ |
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struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
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if (!ratio) { |
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dev->tdm_slots = 0; |
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return 0; |
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} |
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if (ratio > BCM2835_I2S_MAX_FRAME_LENGTH) |
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return -EINVAL; |
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dev->tdm_slots = 2; |
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dev->rx_mask = 0x03; |
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dev->tx_mask = 0x03; |
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dev->slot_width = ratio / 2; |
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dev->frame_length = ratio; |
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return 0; |
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} |
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static int bcm2835_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai, |
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unsigned int tx_mask, unsigned int rx_mask, |
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int slots, int width) |
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{ |
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struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
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if (slots) { |
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if (slots < 0 || width < 0) |
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return -EINVAL; |
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/* Limit masks to available slots */ |
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rx_mask &= GENMASK(slots - 1, 0); |
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tx_mask &= GENMASK(slots - 1, 0); |
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/* |
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* The driver is limited to 2-channel setups. |
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* Check that exactly 2 bits are set in the masks. |
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*/ |
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if (hweight_long((unsigned long) rx_mask) != 2 |
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|| hweight_long((unsigned long) tx_mask) != 2) |
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return -EINVAL; |
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if (slots * width > BCM2835_I2S_MAX_FRAME_LENGTH) |
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return -EINVAL; |
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} |
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dev->tdm_slots = slots; |
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dev->rx_mask = rx_mask; |
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dev->tx_mask = tx_mask; |
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dev->slot_width = width; |
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dev->frame_length = slots * width; |
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return 0; |
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} |
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/* |
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* Convert logical slot number into physical slot number. |
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* |
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* If odd_offset is 0 sequential number is identical to logical number. |
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* This is used for DSP modes with slot numbering 0 1 2 3 ... |
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* |
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* Otherwise odd_offset defines the physical offset for odd numbered |
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* slots. This is used for I2S and left/right justified modes to |
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* translate from logical slot numbers 0 1 2 3 ... into physical slot |
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* numbers 0 2 ... 3 4 ... |
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*/ |
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static int bcm2835_i2s_convert_slot(unsigned int slot, unsigned int odd_offset) |
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{ |
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if (!odd_offset) |
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return slot; |
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if (slot & 1) |
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return (slot >> 1) + odd_offset; |
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return slot >> 1; |
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} |
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/* |
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* Calculate channel position from mask and slot width. |
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* |
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* Mask must contain exactly 2 set bits. |
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* Lowest set bit is channel 1 position, highest set bit channel 2. |
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* The constant offset is added to both channel positions. |
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* |
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* If odd_offset is > 0 slot positions are translated to |
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* I2S-style TDM slot numbering ( 0 2 ... 3 4 ...) with odd |
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* logical slot numbers starting at physical slot odd_offset. |
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*/ |
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static void bcm2835_i2s_calc_channel_pos( |
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unsigned int *ch1_pos, unsigned int *ch2_pos, |
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unsigned int mask, unsigned int width, |
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unsigned int bit_offset, unsigned int odd_offset) |
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{ |
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*ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset) |
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* width + bit_offset; |
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*ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset) |
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* width + bit_offset; |
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} |
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static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
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unsigned int data_length, data_delay, framesync_length; |
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unsigned int slots, slot_width, odd_slot_offset; |
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int frame_length, bclk_rate; |
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unsigned int rx_mask, tx_mask; |
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unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos; |
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unsigned int mode, format; |
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bool bit_clock_master = false; |
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bool frame_sync_master = false; |
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bool frame_start_falling_edge = false; |
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uint32_t csreg; |
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int ret = 0; |
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/* |
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* If a stream is already enabled, |
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* the registers are already set properly. |
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*/ |
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regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg); |
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if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON)) |
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return 0; |
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data_length = params_width(params); |
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data_delay = 0; |
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odd_slot_offset = 0; |
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mode = 0; |
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if (dev->tdm_slots) { |
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slots = dev->tdm_slots; |
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slot_width = dev->slot_width; |
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frame_length = dev->frame_length; |
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rx_mask = dev->rx_mask; |
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tx_mask = dev->tx_mask; |
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bclk_rate = dev->frame_length * params_rate(params); |
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} else { |
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slots = 2; |
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slot_width = params_width(params); |
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rx_mask = 0x03; |
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tx_mask = 0x03; |
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frame_length = snd_soc_params_to_frame_size(params); |
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if (frame_length < 0) |
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return frame_length; |
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bclk_rate = snd_soc_params_to_bclk(params); |
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if (bclk_rate < 0) |
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return bclk_rate; |
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} |
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/* Check if data fits into slots */ |
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if (data_length > slot_width) |
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return -EINVAL; |
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|
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/* Check if CPU is bit clock master */ |
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switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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case SND_SOC_DAIFMT_CBS_CFM: |
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bit_clock_master = true; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFS: |
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case SND_SOC_DAIFMT_CBM_CFM: |
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bit_clock_master = false; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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/* Check if CPU is frame sync master */ |
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switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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case SND_SOC_DAIFMT_CBM_CFS: |
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frame_sync_master = true; |
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break; |
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case SND_SOC_DAIFMT_CBS_CFM: |
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case SND_SOC_DAIFMT_CBM_CFM: |
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frame_sync_master = false; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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/* Clock should only be set up here if CPU is clock master */ |
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if (bit_clock_master && |
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(!dev->clk_prepared || dev->clk_rate != bclk_rate)) { |
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if (dev->clk_prepared) |
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bcm2835_i2s_stop_clock(dev); |
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|
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if (dev->clk_rate != bclk_rate) { |
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ret = clk_set_rate(dev->clk, bclk_rate); |
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if (ret) |
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return ret; |
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dev->clk_rate = bclk_rate; |
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} |
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|
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bcm2835_i2s_start_clock(dev); |
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} |
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|
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/* Setup the frame format */ |
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format = BCM2835_I2S_CHEN; |
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|
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if (data_length >= 24) |
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format |= BCM2835_I2S_CHWEX; |
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|
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format |= BCM2835_I2S_CHWID((data_length-8)&0xf); |
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|
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/* CH2 format is the same as for CH1 */ |
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format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format); |
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|
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switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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/* I2S mode needs an even number of slots */ |
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if (slots & 1) |
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return -EINVAL; |
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|
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/* |
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* Use I2S-style logical slot numbering: even slots |
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* are in first half of frame, odd slots in second half. |
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*/ |
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odd_slot_offset = slots >> 1; |
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|
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/* MSB starts one cycle after frame start */ |
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data_delay = 1; |
|
|
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/* Setup frame sync signal for 50% duty cycle */ |
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framesync_length = frame_length / 2; |
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frame_start_falling_edge = true; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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if (slots & 1) |
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return -EINVAL; |
|
|
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odd_slot_offset = slots >> 1; |
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data_delay = 0; |
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framesync_length = frame_length / 2; |
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frame_start_falling_edge = false; |
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break; |
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case SND_SOC_DAIFMT_RIGHT_J: |
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if (slots & 1) |
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return -EINVAL; |
|
|
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/* Odd frame lengths aren't supported */ |
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if (frame_length & 1) |
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return -EINVAL; |
|
|
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odd_slot_offset = slots >> 1; |
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data_delay = slot_width - data_length; |
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framesync_length = frame_length / 2; |
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frame_start_falling_edge = false; |
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break; |
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case SND_SOC_DAIFMT_DSP_A: |
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data_delay = 1; |
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framesync_length = 1; |
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frame_start_falling_edge = false; |
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break; |
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case SND_SOC_DAIFMT_DSP_B: |
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data_delay = 0; |
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framesync_length = 1; |
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frame_start_falling_edge = false; |
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break; |
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default: |
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return -EINVAL; |
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} |
|
|
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bcm2835_i2s_calc_channel_pos(&rx_ch1_pos, &rx_ch2_pos, |
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rx_mask, slot_width, data_delay, odd_slot_offset); |
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bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos, |
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tx_mask, slot_width, data_delay, odd_slot_offset); |
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|
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/* |
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* Transmitting data immediately after frame start, eg |
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* in left-justified or DSP mode A, only works stable |
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* if bcm2835 is the frame clock master. |
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*/ |
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if ((!rx_ch1_pos || !tx_ch1_pos) && !frame_sync_master) |
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dev_warn(dev->dev, |
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"Unstable slave config detected, L/R may be swapped"); |
|
|
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/* |
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* Set format for both streams. |
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* We cannot set another frame length |
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* (and therefore word length) anyway, |
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* so the format will be the same. |
|
*/ |
|
regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, |
|
format |
|
| BCM2835_I2S_CH1_POS(rx_ch1_pos) |
|
| BCM2835_I2S_CH2_POS(rx_ch2_pos)); |
|
regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, |
|
format |
|
| BCM2835_I2S_CH1_POS(tx_ch1_pos) |
|
| BCM2835_I2S_CH2_POS(tx_ch2_pos)); |
|
|
|
/* Setup the I2S mode */ |
|
|
|
if (data_length <= 16) { |
|
/* |
|
* Use frame packed mode (2 channels per 32 bit word) |
|
* We cannot set another frame length in the second stream |
|
* (and therefore word length) anyway, |
|
* so the format will be the same. |
|
*/ |
|
mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP; |
|
} |
|
|
|
mode |= BCM2835_I2S_FLEN(frame_length - 1); |
|
mode |= BCM2835_I2S_FSLEN(framesync_length); |
|
|
|
/* CLKM selects bcm2835 clock slave mode */ |
|
if (!bit_clock_master) |
|
mode |= BCM2835_I2S_CLKM; |
|
|
|
/* FSM selects bcm2835 frame sync slave mode */ |
|
if (!frame_sync_master) |
|
mode |= BCM2835_I2S_FSM; |
|
|
|
/* CLKI selects normal clocking mode, sampling on rising edge */ |
|
switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) { |
|
case SND_SOC_DAIFMT_NB_NF: |
|
case SND_SOC_DAIFMT_NB_IF: |
|
mode |= BCM2835_I2S_CLKI; |
|
break; |
|
case SND_SOC_DAIFMT_IB_NF: |
|
case SND_SOC_DAIFMT_IB_IF: |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
/* FSI selects frame start on falling edge */ |
|
switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) { |
|
case SND_SOC_DAIFMT_NB_NF: |
|
case SND_SOC_DAIFMT_IB_NF: |
|
if (frame_start_falling_edge) |
|
mode |= BCM2835_I2S_FSI; |
|
break; |
|
case SND_SOC_DAIFMT_NB_IF: |
|
case SND_SOC_DAIFMT_IB_IF: |
|
if (!frame_start_falling_edge) |
|
mode |= BCM2835_I2S_FSI; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode); |
|
|
|
/* Setup the DMA parameters */ |
|
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, |
|
BCM2835_I2S_RXTHR(1) |
|
| BCM2835_I2S_TXTHR(1) |
|
| BCM2835_I2S_DMAEN, 0xffffffff); |
|
|
|
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG, |
|
BCM2835_I2S_TX_PANIC(0x10) |
|
| BCM2835_I2S_RX_PANIC(0x30) |
|
| BCM2835_I2S_TX(0x30) |
|
| BCM2835_I2S_RX(0x20), 0xffffffff); |
|
|
|
/* Clear FIFOs */ |
|
bcm2835_i2s_clear_fifos(dev, true, true); |
|
|
|
dev_dbg(dev->dev, |
|
"slots: %d width: %d rx mask: 0x%02x tx_mask: 0x%02x\n", |
|
slots, slot_width, rx_mask, tx_mask); |
|
|
|
dev_dbg(dev->dev, "frame len: %d sync len: %d data len: %d\n", |
|
frame_length, framesync_length, data_length); |
|
|
|
dev_dbg(dev->dev, "rx pos: %d,%d tx pos: %d,%d\n", |
|
rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos); |
|
|
|
dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n", |
|
params_rate(params), bclk_rate); |
|
|
|
dev_dbg(dev->dev, "CLKM: %d CLKI: %d FSM: %d FSI: %d frame start: %s edge\n", |
|
!!(mode & BCM2835_I2S_CLKM), |
|
!!(mode & BCM2835_I2S_CLKI), |
|
!!(mode & BCM2835_I2S_FSM), |
|
!!(mode & BCM2835_I2S_FSI), |
|
(mode & BCM2835_I2S_FSI) ? "falling" : "rising"); |
|
|
|
return ret; |
|
} |
|
|
|
static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
uint32_t cs_reg; |
|
|
|
/* |
|
* Clear both FIFOs if the one that should be started |
|
* is not empty at the moment. This should only happen |
|
* after overrun. Otherwise, hw_params would have cleared |
|
* the FIFO. |
|
*/ |
|
regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg); |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK |
|
&& !(cs_reg & BCM2835_I2S_TXE)) |
|
bcm2835_i2s_clear_fifos(dev, true, false); |
|
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE |
|
&& (cs_reg & BCM2835_I2S_RXD)) |
|
bcm2835_i2s_clear_fifos(dev, false, true); |
|
|
|
return 0; |
|
} |
|
|
|
static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev, |
|
struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
uint32_t mask; |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
|
mask = BCM2835_I2S_RXON; |
|
else |
|
mask = BCM2835_I2S_TXON; |
|
|
|
regmap_update_bits(dev->i2s_regmap, |
|
BCM2835_I2S_CS_A_REG, mask, 0); |
|
|
|
/* Stop also the clock when not SND_SOC_DAIFMT_CONT */ |
|
if (!snd_soc_dai_active(dai) && !(dev->fmt & SND_SOC_DAIFMT_CONT)) |
|
bcm2835_i2s_stop_clock(dev); |
|
} |
|
|
|
static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
uint32_t mask; |
|
|
|
switch (cmd) { |
|
case SNDRV_PCM_TRIGGER_START: |
|
case SNDRV_PCM_TRIGGER_RESUME: |
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
|
bcm2835_i2s_start_clock(dev); |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
|
mask = BCM2835_I2S_RXON; |
|
else |
|
mask = BCM2835_I2S_TXON; |
|
|
|
regmap_update_bits(dev->i2s_regmap, |
|
BCM2835_I2S_CS_A_REG, mask, mask); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_STOP: |
|
case SNDRV_PCM_TRIGGER_SUSPEND: |
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
|
bcm2835_i2s_stop(dev, substream, dai); |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int bcm2835_i2s_startup(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
|
|
if (snd_soc_dai_active(dai)) |
|
return 0; |
|
|
|
/* Should this still be running stop it */ |
|
bcm2835_i2s_stop_clock(dev); |
|
|
|
/* Enable PCM block */ |
|
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, |
|
BCM2835_I2S_EN, BCM2835_I2S_EN); |
|
|
|
/* |
|
* Disable STBY. |
|
* Requires at least 4 PCM clock cycles to take effect. |
|
*/ |
|
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, |
|
BCM2835_I2S_STBY, BCM2835_I2S_STBY); |
|
|
|
return 0; |
|
} |
|
|
|
static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
|
|
bcm2835_i2s_stop(dev, substream, dai); |
|
|
|
/* If both streams are stopped, disable module and clock */ |
|
if (snd_soc_dai_active(dai)) |
|
return; |
|
|
|
/* Disable the module */ |
|
regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, |
|
BCM2835_I2S_EN, 0); |
|
|
|
/* |
|
* Stopping clock is necessary, because stop does |
|
* not stop the clock when SND_SOC_DAIFMT_CONT |
|
*/ |
|
bcm2835_i2s_stop_clock(dev); |
|
} |
|
|
|
static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = { |
|
.startup = bcm2835_i2s_startup, |
|
.shutdown = bcm2835_i2s_shutdown, |
|
.prepare = bcm2835_i2s_prepare, |
|
.trigger = bcm2835_i2s_trigger, |
|
.hw_params = bcm2835_i2s_hw_params, |
|
.set_fmt = bcm2835_i2s_set_dai_fmt, |
|
.set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio, |
|
.set_tdm_slot = bcm2835_i2s_set_dai_tdm_slot, |
|
}; |
|
|
|
static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai) |
|
{ |
|
struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
|
|
|
snd_soc_dai_init_dma_data(dai, |
|
&dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK], |
|
&dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]); |
|
|
|
return 0; |
|
} |
|
|
|
static struct snd_soc_dai_driver bcm2835_i2s_dai = { |
|
.name = "bcm2835-i2s", |
|
.probe = bcm2835_i2s_dai_probe, |
|
.playback = { |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = SNDRV_PCM_RATE_CONTINUOUS, |
|
.rate_min = 8000, |
|
.rate_max = 384000, |
|
.formats = SNDRV_PCM_FMTBIT_S16_LE |
|
| SNDRV_PCM_FMTBIT_S24_LE |
|
| SNDRV_PCM_FMTBIT_S32_LE |
|
}, |
|
.capture = { |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = SNDRV_PCM_RATE_CONTINUOUS, |
|
.rate_min = 8000, |
|
.rate_max = 384000, |
|
.formats = SNDRV_PCM_FMTBIT_S16_LE |
|
| SNDRV_PCM_FMTBIT_S24_LE |
|
| SNDRV_PCM_FMTBIT_S32_LE |
|
}, |
|
.ops = &bcm2835_i2s_dai_ops, |
|
.symmetric_rate = 1, |
|
.symmetric_sample_bits = 1, |
|
}; |
|
|
|
static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg) |
|
{ |
|
switch (reg) { |
|
case BCM2835_I2S_CS_A_REG: |
|
case BCM2835_I2S_FIFO_A_REG: |
|
case BCM2835_I2S_INTSTC_A_REG: |
|
case BCM2835_I2S_GRAY_REG: |
|
return true; |
|
default: |
|
return false; |
|
} |
|
} |
|
|
|
static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg) |
|
{ |
|
switch (reg) { |
|
case BCM2835_I2S_FIFO_A_REG: |
|
return true; |
|
default: |
|
return false; |
|
} |
|
} |
|
|
|
static const struct regmap_config bcm2835_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.max_register = BCM2835_I2S_GRAY_REG, |
|
.precious_reg = bcm2835_i2s_precious_reg, |
|
.volatile_reg = bcm2835_i2s_volatile_reg, |
|
.cache_type = REGCACHE_RBTREE, |
|
}; |
|
|
|
static const struct snd_soc_component_driver bcm2835_i2s_component = { |
|
.name = "bcm2835-i2s-comp", |
|
}; |
|
|
|
static int bcm2835_i2s_probe(struct platform_device *pdev) |
|
{ |
|
struct bcm2835_i2s_dev *dev; |
|
int ret; |
|
void __iomem *base; |
|
const __be32 *addr; |
|
dma_addr_t dma_base; |
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(*dev), |
|
GFP_KERNEL); |
|
if (!dev) |
|
return -ENOMEM; |
|
|
|
/* get the clock */ |
|
dev->clk_prepared = false; |
|
dev->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(dev->clk)) { |
|
ret = PTR_ERR(dev->clk); |
|
if (ret == -EPROBE_DEFER) |
|
dev_dbg(&pdev->dev, "could not get clk: %d\n", ret); |
|
else |
|
dev_err(&pdev->dev, "could not get clk: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
/* Request ioarea */ |
|
base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
|
|
dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base, |
|
&bcm2835_regmap_config); |
|
if (IS_ERR(dev->i2s_regmap)) |
|
return PTR_ERR(dev->i2s_regmap); |
|
|
|
/* Set the DMA address - we have to parse DT ourselves */ |
|
addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL); |
|
if (!addr) { |
|
dev_err(&pdev->dev, "could not get DMA-register address\n"); |
|
return -EINVAL; |
|
} |
|
dma_base = be32_to_cpup(addr); |
|
|
|
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = |
|
dma_base + BCM2835_I2S_FIFO_A_REG; |
|
|
|
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = |
|
dma_base + BCM2835_I2S_FIFO_A_REG; |
|
|
|
/* Set the bus width */ |
|
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width = |
|
DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width = |
|
DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
|
|
/* Set burst */ |
|
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2; |
|
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2; |
|
|
|
/* |
|
* Set the PACK flag to enable S16_LE support (2 S16_LE values |
|
* packed into 32-bit transfers). |
|
*/ |
|
dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].flags = |
|
SND_DMAENGINE_PCM_DAI_FLAG_PACK; |
|
dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags = |
|
SND_DMAENGINE_PCM_DAI_FLAG_PACK; |
|
|
|
/* Store the pdev */ |
|
dev->dev = &pdev->dev; |
|
dev_set_drvdata(&pdev->dev, dev); |
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, |
|
&bcm2835_i2s_component, &bcm2835_i2s_dai, 1); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id bcm2835_i2s_of_match[] = { |
|
{ .compatible = "brcm,bcm2835-i2s", }, |
|
{}, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match); |
|
|
|
static struct platform_driver bcm2835_i2s_driver = { |
|
.probe = bcm2835_i2s_probe, |
|
.driver = { |
|
.name = "bcm2835-i2s", |
|
.of_match_table = bcm2835_i2s_of_match, |
|
}, |
|
}; |
|
|
|
module_platform_driver(bcm2835_i2s_driver); |
|
|
|
MODULE_ALIAS("platform:bcm2835-i2s"); |
|
MODULE_DESCRIPTION("BCM2835 I2S interface"); |
|
MODULE_AUTHOR("Florian Meier <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|