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664 lines
17 KiB
664 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* HD-audio controller helpers |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/delay.h> |
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#include <linux/export.h> |
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#include <sound/core.h> |
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#include <sound/hdaudio.h> |
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#include <sound/hda_register.h> |
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#include "local.h" |
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/* clear CORB read pointer properly */ |
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static void azx_clear_corbrp(struct hdac_bus *bus) |
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{ |
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int timeout; |
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|
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for (timeout = 1000; timeout > 0; timeout--) { |
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if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST) |
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break; |
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udelay(1); |
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} |
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if (timeout <= 0) |
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dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", |
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snd_hdac_chip_readw(bus, CORBRP)); |
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|
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snd_hdac_chip_writew(bus, CORBRP, 0); |
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for (timeout = 1000; timeout > 0; timeout--) { |
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if (snd_hdac_chip_readw(bus, CORBRP) == 0) |
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break; |
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udelay(1); |
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} |
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if (timeout <= 0) |
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dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", |
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snd_hdac_chip_readw(bus, CORBRP)); |
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} |
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/** |
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* snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers |
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* @bus: HD-audio core bus |
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*/ |
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void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus) |
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{ |
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WARN_ON_ONCE(!bus->rb.area); |
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spin_lock_irq(&bus->reg_lock); |
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/* CORB set up */ |
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bus->corb.addr = bus->rb.addr; |
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bus->corb.buf = (__le32 *)bus->rb.area; |
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snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr); |
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snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr)); |
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/* set the corb size to 256 entries (ULI requires explicitly) */ |
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snd_hdac_chip_writeb(bus, CORBSIZE, 0x02); |
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/* set the corb write pointer to 0 */ |
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snd_hdac_chip_writew(bus, CORBWP, 0); |
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|
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/* reset the corb hw read pointer */ |
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snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST); |
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if (!bus->corbrp_self_clear) |
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azx_clear_corbrp(bus); |
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|
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/* enable corb dma */ |
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snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN); |
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/* RIRB set up */ |
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bus->rirb.addr = bus->rb.addr + 2048; |
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bus->rirb.buf = (__le32 *)(bus->rb.area + 2048); |
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bus->rirb.wp = bus->rirb.rp = 0; |
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memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds)); |
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snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr); |
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snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr)); |
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/* set the rirb size to 256 entries (ULI requires explicitly) */ |
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snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02); |
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/* reset the rirb hw write pointer */ |
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snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST); |
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/* set N=1, get RIRB response interrupt for new entry */ |
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snd_hdac_chip_writew(bus, RINTCNT, 1); |
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/* enable rirb dma and response irq */ |
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snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); |
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/* Accept unsolicited responses */ |
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snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL); |
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spin_unlock_irq(&bus->reg_lock); |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io); |
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/* wait for cmd dmas till they are stopped */ |
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static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus) |
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{ |
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unsigned long timeout; |
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timeout = jiffies + msecs_to_jiffies(100); |
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while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN) |
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&& time_before(jiffies, timeout)) |
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udelay(10); |
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timeout = jiffies + msecs_to_jiffies(100); |
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while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN) |
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&& time_before(jiffies, timeout)) |
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udelay(10); |
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} |
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/** |
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* snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers |
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* @bus: HD-audio core bus |
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*/ |
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void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus) |
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{ |
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spin_lock_irq(&bus->reg_lock); |
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/* disable ringbuffer DMAs */ |
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snd_hdac_chip_writeb(bus, RIRBCTL, 0); |
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snd_hdac_chip_writeb(bus, CORBCTL, 0); |
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spin_unlock_irq(&bus->reg_lock); |
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hdac_wait_for_cmd_dmas(bus); |
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spin_lock_irq(&bus->reg_lock); |
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/* disable unsolicited responses */ |
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snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0); |
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spin_unlock_irq(&bus->reg_lock); |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io); |
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static unsigned int azx_command_addr(u32 cmd) |
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{ |
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unsigned int addr = cmd >> 28; |
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if (snd_BUG_ON(addr >= HDA_MAX_CODECS)) |
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addr = 0; |
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return addr; |
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} |
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/** |
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* snd_hdac_bus_send_cmd - send a command verb via CORB |
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* @bus: HD-audio core bus |
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* @val: encoded verb value to send |
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* |
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* Returns zero for success or a negative error code. |
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*/ |
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int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) |
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{ |
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unsigned int addr = azx_command_addr(val); |
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unsigned int wp, rp; |
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spin_lock_irq(&bus->reg_lock); |
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bus->last_cmd[azx_command_addr(val)] = val; |
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/* add command to corb */ |
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wp = snd_hdac_chip_readw(bus, CORBWP); |
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if (wp == 0xffff) { |
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/* something wrong, controller likely turned to D3 */ |
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spin_unlock_irq(&bus->reg_lock); |
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return -EIO; |
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} |
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wp++; |
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wp %= AZX_MAX_CORB_ENTRIES; |
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rp = snd_hdac_chip_readw(bus, CORBRP); |
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if (wp == rp) { |
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/* oops, it's full */ |
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spin_unlock_irq(&bus->reg_lock); |
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return -EAGAIN; |
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} |
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bus->rirb.cmds[addr]++; |
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bus->corb.buf[wp] = cpu_to_le32(val); |
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snd_hdac_chip_writew(bus, CORBWP, wp); |
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spin_unlock_irq(&bus->reg_lock); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd); |
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#define AZX_RIRB_EX_UNSOL_EV (1<<4) |
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/** |
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* snd_hdac_bus_update_rirb - retrieve RIRB entries |
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* @bus: HD-audio core bus |
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* |
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* Usually called from interrupt handler. |
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* The caller needs bus->reg_lock spinlock before calling this. |
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*/ |
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void snd_hdac_bus_update_rirb(struct hdac_bus *bus) |
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{ |
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unsigned int rp, wp; |
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unsigned int addr; |
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u32 res, res_ex; |
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wp = snd_hdac_chip_readw(bus, RIRBWP); |
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if (wp == 0xffff) { |
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/* something wrong, controller likely turned to D3 */ |
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return; |
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} |
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if (wp == bus->rirb.wp) |
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return; |
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bus->rirb.wp = wp; |
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while (bus->rirb.rp != wp) { |
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bus->rirb.rp++; |
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bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES; |
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rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */ |
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res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]); |
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res = le32_to_cpu(bus->rirb.buf[rp]); |
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addr = res_ex & 0xf; |
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if (addr >= HDA_MAX_CODECS) { |
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dev_err(bus->dev, |
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"spurious response %#x:%#x, rp = %d, wp = %d", |
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res, res_ex, bus->rirb.rp, wp); |
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snd_BUG(); |
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} else if (res_ex & AZX_RIRB_EX_UNSOL_EV) |
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snd_hdac_bus_queue_event(bus, res, res_ex); |
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else if (bus->rirb.cmds[addr]) { |
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bus->rirb.res[addr] = res; |
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bus->rirb.cmds[addr]--; |
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if (!bus->rirb.cmds[addr] && |
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waitqueue_active(&bus->rirb_wq)) |
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wake_up(&bus->rirb_wq); |
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} else { |
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dev_err_ratelimited(bus->dev, |
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"spurious response %#x:%#x, last cmd=%#08x\n", |
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res, res_ex, bus->last_cmd[addr]); |
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} |
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} |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb); |
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/** |
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* snd_hdac_bus_get_response - receive a response via RIRB |
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* @bus: HD-audio core bus |
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* @addr: codec address |
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* @res: pointer to store the value, NULL when not needed |
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* |
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* Returns zero if a value is read, or a negative error code. |
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*/ |
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int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, |
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unsigned int *res) |
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{ |
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unsigned long timeout; |
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unsigned long loopcounter; |
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wait_queue_entry_t wait; |
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bool warned = false; |
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init_wait_entry(&wait, 0); |
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timeout = jiffies + msecs_to_jiffies(1000); |
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for (loopcounter = 0;; loopcounter++) { |
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spin_lock_irq(&bus->reg_lock); |
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if (!bus->polling_mode) |
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prepare_to_wait(&bus->rirb_wq, &wait, |
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TASK_UNINTERRUPTIBLE); |
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if (bus->polling_mode) |
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snd_hdac_bus_update_rirb(bus); |
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if (!bus->rirb.cmds[addr]) { |
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if (res) |
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*res = bus->rirb.res[addr]; /* the last value */ |
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if (!bus->polling_mode) |
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finish_wait(&bus->rirb_wq, &wait); |
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spin_unlock_irq(&bus->reg_lock); |
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return 0; |
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} |
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spin_unlock_irq(&bus->reg_lock); |
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if (time_after(jiffies, timeout)) |
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break; |
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#define LOOP_COUNT_MAX 3000 |
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if (!bus->polling_mode) { |
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schedule_timeout(msecs_to_jiffies(2)); |
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} else if (bus->needs_damn_long_delay || |
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loopcounter > LOOP_COUNT_MAX) { |
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if (loopcounter > LOOP_COUNT_MAX && !warned) { |
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dev_dbg_ratelimited(bus->dev, |
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"too slow response, last cmd=%#08x\n", |
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bus->last_cmd[addr]); |
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warned = true; |
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} |
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msleep(2); /* temporary workaround */ |
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} else { |
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udelay(10); |
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cond_resched(); |
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} |
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} |
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if (!bus->polling_mode) |
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finish_wait(&bus->rirb_wq, &wait); |
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return -EIO; |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response); |
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#define HDAC_MAX_CAPS 10 |
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/** |
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* snd_hdac_bus_parse_capabilities - parse capability structure |
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* @bus: the pointer to bus object |
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* |
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* Returns 0 if successful, or a negative error code. |
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*/ |
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int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus) |
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{ |
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unsigned int cur_cap; |
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unsigned int offset; |
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unsigned int counter = 0; |
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offset = snd_hdac_chip_readw(bus, LLCH); |
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/* Lets walk the linked capabilities list */ |
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do { |
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cur_cap = _snd_hdac_chip_readl(bus, offset); |
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dev_dbg(bus->dev, "Capability version: 0x%x\n", |
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(cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF); |
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dev_dbg(bus->dev, "HDA capability ID: 0x%x\n", |
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(cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF); |
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if (cur_cap == -1) { |
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dev_dbg(bus->dev, "Invalid capability reg read\n"); |
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break; |
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} |
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switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) { |
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case AZX_ML_CAP_ID: |
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dev_dbg(bus->dev, "Found ML capability\n"); |
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bus->mlcap = bus->remap_addr + offset; |
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break; |
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case AZX_GTS_CAP_ID: |
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dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset); |
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bus->gtscap = bus->remap_addr + offset; |
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break; |
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case AZX_PP_CAP_ID: |
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/* PP capability found, the Audio DSP is present */ |
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dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset); |
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bus->ppcap = bus->remap_addr + offset; |
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break; |
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case AZX_SPB_CAP_ID: |
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/* SPIB capability found, handler function */ |
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dev_dbg(bus->dev, "Found SPB capability\n"); |
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bus->spbcap = bus->remap_addr + offset; |
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break; |
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|
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case AZX_DRSM_CAP_ID: |
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/* DMA resume capability found, handler function */ |
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dev_dbg(bus->dev, "Found DRSM capability\n"); |
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bus->drsmcap = bus->remap_addr + offset; |
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break; |
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default: |
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dev_err(bus->dev, "Unknown capability %d\n", cur_cap); |
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cur_cap = 0; |
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break; |
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} |
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counter++; |
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if (counter > HDAC_MAX_CAPS) { |
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dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n"); |
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break; |
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} |
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/* read the offset of next capability */ |
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offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK; |
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} while (offset); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities); |
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/* |
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* Lowlevel interface |
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*/ |
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/** |
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* snd_hdac_bus_enter_link_reset - enter link reset |
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* @bus: HD-audio core bus |
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* |
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* Enter to the link reset state. |
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*/ |
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void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus) |
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{ |
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unsigned long timeout; |
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/* reset controller */ |
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snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0); |
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timeout = jiffies + msecs_to_jiffies(100); |
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while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) && |
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time_before(jiffies, timeout)) |
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usleep_range(500, 1000); |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset); |
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|
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/** |
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* snd_hdac_bus_exit_link_reset - exit link reset |
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* @bus: HD-audio core bus |
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* |
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* Exit from the link reset state. |
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*/ |
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void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus) |
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{ |
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unsigned long timeout; |
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snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET); |
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timeout = jiffies + msecs_to_jiffies(100); |
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while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout)) |
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usleep_range(500, 1000); |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset); |
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/* reset codec link */ |
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int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset) |
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{ |
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if (!full_reset) |
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goto skip_reset; |
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|
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/* clear STATESTS */ |
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snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); |
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|
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/* reset controller */ |
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snd_hdac_bus_enter_link_reset(bus); |
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|
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/* delay for >= 100us for codec PLL to settle per spec |
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* Rev 0.9 section 5.5.1 |
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*/ |
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usleep_range(500, 1000); |
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|
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/* Bring controller out of reset */ |
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snd_hdac_bus_exit_link_reset(bus); |
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|
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/* Brent Chartrand said to wait >= 540us for codecs to initialize */ |
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usleep_range(1000, 1200); |
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|
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skip_reset: |
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/* check to see if controller is ready */ |
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if (!snd_hdac_chip_readb(bus, GCTL)) { |
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dev_dbg(bus->dev, "controller not ready!\n"); |
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return -EBUSY; |
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} |
|
|
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/* detect codecs */ |
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if (!bus->codec_mask) { |
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bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS); |
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dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask); |
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} |
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|
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link); |
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|
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/* enable interrupts */ |
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static void azx_int_enable(struct hdac_bus *bus) |
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{ |
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/* enable controller CIE and GIE */ |
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snd_hdac_chip_updatel(bus, INTCTL, |
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AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, |
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AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN); |
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} |
|
|
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/* disable interrupts */ |
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static void azx_int_disable(struct hdac_bus *bus) |
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{ |
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struct hdac_stream *azx_dev; |
|
|
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/* disable interrupts in stream descriptor */ |
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list_for_each_entry(azx_dev, &bus->stream_list, list) |
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snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0); |
|
|
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/* disable SIE for all streams */ |
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snd_hdac_chip_writeb(bus, INTCTL, 0); |
|
|
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/* disable controller CIE and GIE */ |
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snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0); |
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} |
|
|
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/* clear interrupts */ |
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static void azx_int_clear(struct hdac_bus *bus) |
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{ |
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struct hdac_stream *azx_dev; |
|
|
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/* clear stream status */ |
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list_for_each_entry(azx_dev, &bus->stream_list, list) |
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snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); |
|
|
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/* clear STATESTS */ |
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snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); |
|
|
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/* clear rirb status */ |
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snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); |
|
|
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/* clear int status */ |
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snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM); |
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} |
|
|
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/** |
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* snd_hdac_bus_init_chip - reset and start the controller registers |
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* @bus: HD-audio core bus |
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* @full_reset: Do full reset |
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*/ |
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bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset) |
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{ |
|
if (bus->chip_init) |
|
return false; |
|
|
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/* reset controller */ |
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snd_hdac_bus_reset_link(bus, full_reset); |
|
|
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/* clear interrupts */ |
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azx_int_clear(bus); |
|
|
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/* initialize the codec command I/O */ |
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snd_hdac_bus_init_cmd_io(bus); |
|
|
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/* enable interrupts after CORB/RIRB buffers are initialized above */ |
|
azx_int_enable(bus); |
|
|
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/* program the position buffer */ |
|
if (bus->use_posbuf && bus->posbuf.addr) { |
|
snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr); |
|
snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr)); |
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} |
|
|
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bus->chip_init = true; |
|
|
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return true; |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip); |
|
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/** |
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* snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os |
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* @bus: HD-audio core bus |
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*/ |
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void snd_hdac_bus_stop_chip(struct hdac_bus *bus) |
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{ |
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if (!bus->chip_init) |
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return; |
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|
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/* disable interrupts */ |
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azx_int_disable(bus); |
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azx_int_clear(bus); |
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|
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/* disable CORB/RIRB */ |
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snd_hdac_bus_stop_cmd_io(bus); |
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|
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/* disable position buffer */ |
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if (bus->posbuf.addr) { |
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snd_hdac_chip_writel(bus, DPLBASE, 0); |
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snd_hdac_chip_writel(bus, DPUBASE, 0); |
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} |
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|
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bus->chip_init = false; |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip); |
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|
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/** |
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* snd_hdac_bus_handle_stream_irq - interrupt handler for streams |
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* @bus: HD-audio core bus |
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* @status: INTSTS register value |
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* @ack: callback to be called for woken streams |
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* |
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* Returns the bits of handled streams, or zero if no stream is handled. |
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*/ |
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int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, |
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void (*ack)(struct hdac_bus *, |
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struct hdac_stream *)) |
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{ |
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struct hdac_stream *azx_dev; |
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u8 sd_status; |
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int handled = 0; |
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|
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list_for_each_entry(azx_dev, &bus->stream_list, list) { |
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if (status & azx_dev->sd_int_sta_mask) { |
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sd_status = snd_hdac_stream_readb(azx_dev, SD_STS); |
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snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); |
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handled |= 1 << azx_dev->index; |
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if (!azx_dev->substream || !azx_dev->running || |
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!(sd_status & SD_INT_COMPLETE)) |
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continue; |
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if (ack) |
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ack(bus, azx_dev); |
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} |
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} |
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return handled; |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq); |
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|
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/** |
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* snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers |
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* @bus: HD-audio core bus |
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* |
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* Call this after assigning the all streams. |
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* Returns zero for success, or a negative error code. |
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*/ |
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int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus) |
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{ |
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struct hdac_stream *s; |
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int num_streams = 0; |
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int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV; |
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int err; |
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|
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list_for_each_entry(s, &bus->stream_list, list) { |
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/* allocate memory for the BDL for each stream */ |
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err = snd_dma_alloc_pages(dma_type, bus->dev, |
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BDL_SIZE, &s->bdl); |
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num_streams++; |
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if (err < 0) |
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return -ENOMEM; |
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} |
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|
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if (WARN_ON(!num_streams)) |
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return -EINVAL; |
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/* allocate memory for the position buffer */ |
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err = snd_dma_alloc_pages(dma_type, bus->dev, |
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num_streams * 8, &bus->posbuf); |
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if (err < 0) |
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return -ENOMEM; |
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list_for_each_entry(s, &bus->stream_list, list) |
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s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8); |
|
|
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/* single page (at least 4096 bytes) must suffice for both ringbuffes */ |
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return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb); |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages); |
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|
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/** |
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* snd_hdac_bus_free_stream_pages - release BDL and other buffers |
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* @bus: HD-audio core bus |
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*/ |
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void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus) |
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{ |
|
struct hdac_stream *s; |
|
|
|
list_for_each_entry(s, &bus->stream_list, list) { |
|
if (s->bdl.area) |
|
snd_dma_free_pages(&s->bdl); |
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} |
|
|
|
if (bus->rb.area) |
|
snd_dma_free_pages(&bus->rb); |
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if (bus->posbuf.area) |
|
snd_dma_free_pages(&bus->posbuf); |
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} |
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EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages); |
|
|
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/** |
|
* snd_hdac_bus_link_power - power up/down codec link |
|
* @codec: HD-audio device |
|
* @enable: whether to power-up the link |
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*/ |
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void snd_hdac_bus_link_power(struct hdac_device *codec, bool enable) |
|
{ |
|
if (enable) |
|
set_bit(codec->addr, &codec->bus->codec_powered); |
|
else |
|
clear_bit(codec->addr, &codec->bus->codec_powered); |
|
} |
|
EXPORT_SYMBOL_GPL(snd_hdac_bus_link_power);
|
|
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