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427 lines
13 KiB
427 lines
13 KiB
/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- |
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* Created: Tue Jan 25 01:50:01 1999 by [email protected] |
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* |
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. |
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. |
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* All rights reserved. |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice (including the next |
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* paragraph) shall be included in all copies or substantial portions of the |
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* Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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* |
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* Authors: |
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* Jeff Hartmann <[email protected]> |
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* Keith Whitwell <[email protected]> |
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* |
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* Rewritten by: |
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* Gareth Hughes <[email protected]> |
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*/ |
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#ifndef __MGA_DRM_H__ |
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#define __MGA_DRM_H__ |
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#include "drm.h" |
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#if defined(__cplusplus) |
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extern "C" { |
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#endif |
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/* WARNING: If you change any of these defines, make sure to change the |
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* defines in the Xserver file (mga_sarea.h) |
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*/ |
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#ifndef __MGA_SAREA_DEFINES__ |
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#define __MGA_SAREA_DEFINES__ |
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/* WARP pipe flags |
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*/ |
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#define MGA_F 0x1 /* fog */ |
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#define MGA_A 0x2 /* alpha */ |
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#define MGA_S 0x4 /* specular */ |
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#define MGA_T2 0x8 /* multitexture */ |
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#define MGA_WARP_TGZ 0 |
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#define MGA_WARP_TGZF (MGA_F) |
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#define MGA_WARP_TGZA (MGA_A) |
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#define MGA_WARP_TGZAF (MGA_F|MGA_A) |
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#define MGA_WARP_TGZS (MGA_S) |
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#define MGA_WARP_TGZSF (MGA_S|MGA_F) |
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#define MGA_WARP_TGZSA (MGA_S|MGA_A) |
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#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) |
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#define MGA_WARP_T2GZ (MGA_T2) |
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#define MGA_WARP_T2GZF (MGA_T2|MGA_F) |
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#define MGA_WARP_T2GZA (MGA_T2|MGA_A) |
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#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) |
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#define MGA_WARP_T2GZS (MGA_T2|MGA_S) |
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#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) |
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#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) |
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#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) |
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#define MGA_MAX_G200_PIPES 8 /* no multitex */ |
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#define MGA_MAX_G400_PIPES 16 |
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#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES |
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#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ |
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#define MGA_CARD_TYPE_G200 1 |
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#define MGA_CARD_TYPE_G400 2 |
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#define MGA_CARD_TYPE_G450 3 /* not currently used */ |
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#define MGA_CARD_TYPE_G550 4 |
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#define MGA_FRONT 0x1 |
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#define MGA_BACK 0x2 |
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#define MGA_DEPTH 0x4 |
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/* What needs to be changed for the current vertex dma buffer? |
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*/ |
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#define MGA_UPLOAD_CONTEXT 0x1 |
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#define MGA_UPLOAD_TEX0 0x2 |
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#define MGA_UPLOAD_TEX1 0x4 |
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#define MGA_UPLOAD_PIPE 0x8 |
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#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ |
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#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ |
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#define MGA_UPLOAD_2D 0x40 |
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#define MGA_WAIT_AGE 0x80 /* handled client-side */ |
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#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ |
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#if 0 |
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#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock |
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quiescent */ |
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#endif |
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/* 32 buffers of 64k each, total 2 meg. |
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*/ |
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#define MGA_BUFFER_SIZE (1 << 16) |
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#define MGA_NUM_BUFFERS 128 |
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/* Keep these small for testing. |
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*/ |
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#define MGA_NR_SAREA_CLIPRECTS 8 |
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/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 |
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* regions, subject to a minimum region size of (1<<16) == 64k. |
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* |
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* Clients may subdivide regions internally, but when sharing between |
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* clients, the region size is the minimum granularity. |
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*/ |
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#define MGA_CARD_HEAP 0 |
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#define MGA_AGP_HEAP 1 |
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#define MGA_NR_TEX_HEAPS 2 |
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#define MGA_NR_TEX_REGIONS 16 |
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#define MGA_LOG_MIN_TEX_REGION_SIZE 16 |
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#define DRM_MGA_IDLE_RETRY 2048 |
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#endif /* __MGA_SAREA_DEFINES__ */ |
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/* Setup registers for 3D context |
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*/ |
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typedef struct { |
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unsigned int dstorg; |
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unsigned int maccess; |
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unsigned int plnwt; |
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unsigned int dwgctl; |
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unsigned int alphactrl; |
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unsigned int fogcolor; |
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unsigned int wflag; |
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unsigned int tdualstage0; |
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unsigned int tdualstage1; |
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unsigned int fcol; |
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unsigned int stencil; |
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unsigned int stencilctl; |
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} drm_mga_context_regs_t; |
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/* Setup registers for 2D, X server |
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*/ |
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typedef struct { |
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unsigned int pitch; |
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} drm_mga_server_regs_t; |
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/* Setup registers for each texture unit |
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*/ |
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typedef struct { |
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unsigned int texctl; |
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unsigned int texctl2; |
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unsigned int texfilter; |
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unsigned int texbordercol; |
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unsigned int texorg; |
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unsigned int texwidth; |
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unsigned int texheight; |
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unsigned int texorg1; |
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unsigned int texorg2; |
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unsigned int texorg3; |
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unsigned int texorg4; |
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} drm_mga_texture_regs_t; |
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/* General aging mechanism |
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*/ |
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typedef struct { |
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unsigned int head; /* Position of head pointer */ |
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unsigned int wrap; /* Primary DMA wrap count */ |
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} drm_mga_age_t; |
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typedef struct _drm_mga_sarea { |
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/* The channel for communication of state information to the kernel |
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* on firing a vertex dma buffer. |
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*/ |
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drm_mga_context_regs_t context_state; |
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drm_mga_server_regs_t server_state; |
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drm_mga_texture_regs_t tex_state[2]; |
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unsigned int warp_pipe; |
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unsigned int dirty; |
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unsigned int vertsize; |
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/* The current cliprects, or a subset thereof. |
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*/ |
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struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; |
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unsigned int nbox; |
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/* Information about the most recently used 3d drawable. The |
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* client fills in the req_* fields, the server fills in the |
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* exported_ fields and puts the cliprects into boxes, above. |
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* |
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* The client clears the exported_drawable field before |
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* clobbering the boxes data. |
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*/ |
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unsigned int req_drawable; /* the X drawable id */ |
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unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ |
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unsigned int exported_drawable; |
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unsigned int exported_index; |
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unsigned int exported_stamp; |
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unsigned int exported_buffers; |
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unsigned int exported_nfront; |
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unsigned int exported_nback; |
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int exported_back_x, exported_front_x, exported_w; |
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int exported_back_y, exported_front_y, exported_h; |
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struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; |
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/* Counters for aging textures and for client-side throttling. |
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*/ |
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unsigned int status[4]; |
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unsigned int last_wrap; |
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drm_mga_age_t last_frame; |
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unsigned int last_enqueue; /* last time a buffer was enqueued */ |
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unsigned int last_dispatch; /* age of the most recently dispatched buffer */ |
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unsigned int last_quiescent; /* */ |
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/* LRU lists for texture memory in agp space and on the card. |
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*/ |
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struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; |
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unsigned int texAge[MGA_NR_TEX_HEAPS]; |
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/* Mechanism to validate card state. |
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*/ |
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int ctxOwner; |
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} drm_mga_sarea_t; |
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/* MGA specific ioctls |
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* The device specific ioctl range is 0x40 to 0x79. |
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*/ |
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#define DRM_MGA_INIT 0x00 |
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#define DRM_MGA_FLUSH 0x01 |
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#define DRM_MGA_RESET 0x02 |
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#define DRM_MGA_SWAP 0x03 |
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#define DRM_MGA_CLEAR 0x04 |
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#define DRM_MGA_VERTEX 0x05 |
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#define DRM_MGA_INDICES 0x06 |
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#define DRM_MGA_ILOAD 0x07 |
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#define DRM_MGA_BLIT 0x08 |
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#define DRM_MGA_GETPARAM 0x09 |
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/* 3.2: |
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* ioctls for operating on fences. |
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*/ |
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#define DRM_MGA_SET_FENCE 0x0a |
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#define DRM_MGA_WAIT_FENCE 0x0b |
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#define DRM_MGA_DMA_BOOTSTRAP 0x0c |
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#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) |
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#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock) |
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#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) |
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#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) |
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#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) |
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#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) |
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#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) |
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#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) |
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#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) |
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#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) |
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#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32) |
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#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32) |
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#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) |
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typedef struct _drm_mga_warp_index { |
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int installed; |
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unsigned long phys_addr; |
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int size; |
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} drm_mga_warp_index_t; |
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typedef struct drm_mga_init { |
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enum { |
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MGA_INIT_DMA = 0x01, |
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MGA_CLEANUP_DMA = 0x02 |
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} func; |
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unsigned long sarea_priv_offset; |
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int chipset; |
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int sgram; |
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unsigned int maccess; |
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unsigned int fb_cpp; |
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unsigned int front_offset, front_pitch; |
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unsigned int back_offset, back_pitch; |
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unsigned int depth_cpp; |
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unsigned int depth_offset, depth_pitch; |
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unsigned int texture_offset[MGA_NR_TEX_HEAPS]; |
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unsigned int texture_size[MGA_NR_TEX_HEAPS]; |
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unsigned long fb_offset; |
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unsigned long mmio_offset; |
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unsigned long status_offset; |
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unsigned long warp_offset; |
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unsigned long primary_offset; |
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unsigned long buffers_offset; |
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} drm_mga_init_t; |
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typedef struct drm_mga_dma_bootstrap { |
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/** |
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* \name AGP texture region |
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* |
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* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will |
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* be filled in with the actual AGP texture settings. |
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* |
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* \warning |
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* If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode |
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* is zero, it means that PCI memory (most likely through the use of |
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* an IOMMU) is being used for "AGP" textures. |
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*/ |
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/*@{ */ |
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unsigned long texture_handle; /**< Handle used to map AGP textures. */ |
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__u32 texture_size; /**< Size of the AGP texture region. */ |
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/*@} */ |
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/** |
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* Requested size of the primary DMA region. |
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* |
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* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be |
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* filled in with the actual AGP mode. If AGP was not available |
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*/ |
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__u32 primary_size; |
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/** |
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* Requested number of secondary DMA buffers. |
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* |
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* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be |
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* filled in with the actual number of secondary DMA buffers |
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* allocated. Particularly when PCI DMA is used, this may be |
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* (subtantially) less than the number requested. |
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*/ |
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__u32 secondary_bin_count; |
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/** |
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* Requested size of each secondary DMA buffer. |
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* |
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* While the kernel \b is free to reduce |
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* dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed |
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* to reduce dma_mga_dma_bootstrap::secondary_bin_size. |
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*/ |
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__u32 secondary_bin_size; |
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/** |
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* Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, |
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* \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is |
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* zero, it means that PCI DMA should be used, even if AGP is |
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* possible. |
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* |
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* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be |
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* filled in with the actual AGP mode. If AGP was not available |
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* (i.e., PCI DMA was used), this value will be zero. |
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*/ |
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__u32 agp_mode; |
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/** |
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* Desired AGP GART size, measured in megabytes. |
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*/ |
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__u8 agp_size; |
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} drm_mga_dma_bootstrap_t; |
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typedef struct drm_mga_clear { |
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unsigned int flags; |
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unsigned int clear_color; |
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unsigned int clear_depth; |
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unsigned int color_mask; |
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unsigned int depth_mask; |
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} drm_mga_clear_t; |
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typedef struct drm_mga_vertex { |
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int idx; /* buffer to queue */ |
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int used; /* bytes in use */ |
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int discard; /* client finished with buffer? */ |
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} drm_mga_vertex_t; |
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typedef struct drm_mga_indices { |
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int idx; /* buffer to queue */ |
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unsigned int start; |
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unsigned int end; |
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int discard; /* client finished with buffer? */ |
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} drm_mga_indices_t; |
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typedef struct drm_mga_iload { |
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int idx; |
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unsigned int dstorg; |
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unsigned int length; |
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} drm_mga_iload_t; |
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typedef struct _drm_mga_blit { |
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unsigned int planemask; |
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unsigned int srcorg; |
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unsigned int dstorg; |
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int src_pitch, dst_pitch; |
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int delta_sx, delta_sy; |
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int delta_dx, delta_dy; |
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int height, ydir; /* flip image vertically */ |
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int source_pitch, dest_pitch; |
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} drm_mga_blit_t; |
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/* 3.1: An ioctl to get parameters that aren't available to the 3d |
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* client any other way. |
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*/ |
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#define MGA_PARAM_IRQ_NR 1 |
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/* 3.2: Query the actual card type. The DDX only distinguishes between |
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* G200 chips and non-G200 chips, which it calls G400. It turns out that |
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* there are some very sublte differences between the G4x0 chips and the G550 |
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* chips. Using this parameter query, a client-side driver can detect the |
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* difference between a G4x0 and a G550. |
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*/ |
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#define MGA_PARAM_CARD_TYPE 2 |
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typedef struct drm_mga_getparam { |
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int param; |
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void __user *value; |
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} drm_mga_getparam_t; |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif
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