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176 lines
4.9 KiB
176 lines
4.9 KiB
/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */ |
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/* Copyright 2017-2018 Qiang Yu <[email protected]> */ |
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#ifndef __LIMA_DRM_H__ |
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#define __LIMA_DRM_H__ |
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#include "drm.h" |
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#if defined(__cplusplus) |
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extern "C" { |
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#endif |
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enum drm_lima_param_gpu_id { |
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DRM_LIMA_PARAM_GPU_ID_UNKNOWN, |
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DRM_LIMA_PARAM_GPU_ID_MALI400, |
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DRM_LIMA_PARAM_GPU_ID_MALI450, |
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}; |
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enum drm_lima_param { |
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DRM_LIMA_PARAM_GPU_ID, |
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DRM_LIMA_PARAM_NUM_PP, |
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DRM_LIMA_PARAM_GP_VERSION, |
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DRM_LIMA_PARAM_PP_VERSION, |
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}; |
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/** |
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* get various information of the GPU |
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*/ |
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struct drm_lima_get_param { |
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__u32 param; /* in, value in enum drm_lima_param */ |
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__u32 pad; /* pad, must be zero */ |
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__u64 value; /* out, parameter value */ |
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}; |
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/* |
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* heap buffer dynamically increase backup memory size when GP task fail |
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* due to lack of heap memory. size field of heap buffer is an up bound of |
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* the backup memory which can be set to a fairly large value. |
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*/ |
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#define LIMA_BO_FLAG_HEAP (1 << 0) |
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/** |
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* create a buffer for used by GPU |
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*/ |
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struct drm_lima_gem_create { |
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__u32 size; /* in, buffer size */ |
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__u32 flags; /* in, buffer flags */ |
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__u32 handle; /* out, GEM buffer handle */ |
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__u32 pad; /* pad, must be zero */ |
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}; |
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/** |
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* get information of a buffer |
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*/ |
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struct drm_lima_gem_info { |
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__u32 handle; /* in, GEM buffer handle */ |
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__u32 va; /* out, virtual address mapped into GPU MMU */ |
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__u64 offset; /* out, used to mmap this buffer to CPU */ |
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}; |
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#define LIMA_SUBMIT_BO_READ 0x01 |
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#define LIMA_SUBMIT_BO_WRITE 0x02 |
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/* buffer information used by one task */ |
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struct drm_lima_gem_submit_bo { |
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__u32 handle; /* in, GEM buffer handle */ |
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__u32 flags; /* in, buffer read/write by GPU */ |
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}; |
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#define LIMA_GP_FRAME_REG_NUM 6 |
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/* frame used to setup GP for each task */ |
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struct drm_lima_gp_frame { |
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__u32 frame[LIMA_GP_FRAME_REG_NUM]; |
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}; |
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#define LIMA_PP_FRAME_REG_NUM 23 |
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#define LIMA_PP_WB_REG_NUM 12 |
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/* frame used to setup mali400 GPU PP for each task */ |
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struct drm_lima_m400_pp_frame { |
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__u32 frame[LIMA_PP_FRAME_REG_NUM]; |
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__u32 num_pp; |
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__u32 wb[3 * LIMA_PP_WB_REG_NUM]; |
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__u32 plbu_array_address[4]; |
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__u32 fragment_stack_address[4]; |
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}; |
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/* frame used to setup mali450 GPU PP for each task */ |
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struct drm_lima_m450_pp_frame { |
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__u32 frame[LIMA_PP_FRAME_REG_NUM]; |
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__u32 num_pp; |
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__u32 wb[3 * LIMA_PP_WB_REG_NUM]; |
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__u32 use_dlbu; |
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__u32 _pad; |
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union { |
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__u32 plbu_array_address[8]; |
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__u32 dlbu_regs[4]; |
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}; |
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__u32 fragment_stack_address[8]; |
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}; |
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#define LIMA_PIPE_GP 0x00 |
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#define LIMA_PIPE_PP 0x01 |
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#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0) |
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/** |
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* submit a task to GPU |
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* |
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* User can always merge multi sync_file and drm_syncobj |
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* into one drm_syncobj as in_sync[0], but we reserve |
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* in_sync[1] for another task's out_sync to avoid the |
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* export/import/merge pass when explicit sync. |
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*/ |
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struct drm_lima_gem_submit { |
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__u32 ctx; /* in, context handle task is submitted to */ |
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__u32 pipe; /* in, which pipe to use, GP/PP */ |
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__u32 nr_bos; /* in, array length of bos field */ |
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__u32 frame_size; /* in, size of frame field */ |
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__u64 bos; /* in, array of drm_lima_gem_submit_bo */ |
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__u64 frame; /* in, GP/PP frame */ |
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__u32 flags; /* in, submit flags */ |
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__u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */ |
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__u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */ |
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}; |
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#define LIMA_GEM_WAIT_READ 0x01 |
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#define LIMA_GEM_WAIT_WRITE 0x02 |
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/** |
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* wait pending GPU task finish of a buffer |
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*/ |
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struct drm_lima_gem_wait { |
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__u32 handle; /* in, GEM buffer handle */ |
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__u32 op; /* in, CPU want to read/write this buffer */ |
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__s64 timeout_ns; /* in, wait timeout in absulute time */ |
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}; |
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/** |
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* create a context |
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*/ |
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struct drm_lima_ctx_create { |
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__u32 id; /* out, context handle */ |
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__u32 _pad; /* pad, must be zero */ |
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}; |
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/** |
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* free a context |
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*/ |
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struct drm_lima_ctx_free { |
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__u32 id; /* in, context handle */ |
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__u32 _pad; /* pad, must be zero */ |
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}; |
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#define DRM_LIMA_GET_PARAM 0x00 |
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#define DRM_LIMA_GEM_CREATE 0x01 |
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#define DRM_LIMA_GEM_INFO 0x02 |
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#define DRM_LIMA_GEM_SUBMIT 0x03 |
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#define DRM_LIMA_GEM_WAIT 0x04 |
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#define DRM_LIMA_CTX_CREATE 0x05 |
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#define DRM_LIMA_CTX_FREE 0x06 |
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#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param) |
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#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create) |
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#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info) |
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#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit) |
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#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait) |
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#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create) |
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#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free) |
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#if defined(__cplusplus) |
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} |
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#endif |
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#endif /* __LIMA_DRM_H__ */
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