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272 lines
8.7 KiB
272 lines
8.7 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. |
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* |
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* Authors: Shlomi Gridish <[email protected]> |
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* Li Yang <[email protected]> |
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* |
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* Description: |
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* Internal header file for UCC SLOW unit routines. |
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*/ |
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#ifndef __UCC_SLOW_H__ |
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#define __UCC_SLOW_H__ |
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#include <linux/kernel.h> |
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#include <soc/fsl/qe/immap_qe.h> |
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#include <soc/fsl/qe/qe.h> |
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#include <soc/fsl/qe/ucc.h> |
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/* transmit BD's status */ |
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#define T_R 0x80000000 /* ready bit */ |
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#define T_PAD 0x40000000 /* add pads to short frames */ |
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#define T_W 0x20000000 /* wrap bit */ |
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#define T_I 0x10000000 /* interrupt on completion */ |
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#define T_L 0x08000000 /* last */ |
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#define T_A 0x04000000 /* Address - the data transmitted as address |
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chars */ |
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#define T_TC 0x04000000 /* transmit CRC */ |
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#define T_CM 0x02000000 /* continuous mode */ |
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#define T_DEF 0x02000000 /* collision on previous attempt to transmit */ |
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#define T_P 0x01000000 /* Preamble - send Preamble sequence before |
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data */ |
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#define T_HB 0x01000000 /* heartbeat */ |
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#define T_NS 0x00800000 /* No Stop */ |
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#define T_LC 0x00800000 /* late collision */ |
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#define T_RL 0x00400000 /* retransmission limit */ |
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#define T_UN 0x00020000 /* underrun */ |
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#define T_CT 0x00010000 /* CTS lost */ |
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#define T_CSL 0x00010000 /* carrier sense lost */ |
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#define T_RC 0x003c0000 /* retry count */ |
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/* Receive BD's status */ |
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#define R_E 0x80000000 /* buffer empty */ |
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#define R_W 0x20000000 /* wrap bit */ |
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#define R_I 0x10000000 /* interrupt on reception */ |
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#define R_L 0x08000000 /* last */ |
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#define R_C 0x08000000 /* the last byte in this buffer is a cntl |
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char */ |
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#define R_F 0x04000000 /* first */ |
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#define R_A 0x04000000 /* the first byte in this buffer is address |
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byte */ |
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#define R_CM 0x02000000 /* continuous mode */ |
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#define R_ID 0x01000000 /* buffer close on reception of idles */ |
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#define R_M 0x01000000 /* Frame received because of promiscuous |
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mode */ |
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#define R_AM 0x00800000 /* Address match */ |
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#define R_DE 0x00800000 /* Address match */ |
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#define R_LG 0x00200000 /* Break received */ |
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#define R_BR 0x00200000 /* Frame length violation */ |
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#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */ |
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#define R_FR 0x00100000 /* Framing Error (no stop bit) character |
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received */ |
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#define R_PR 0x00080000 /* Parity Error character received */ |
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#define R_AB 0x00080000 /* Frame Aborted */ |
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#define R_SH 0x00080000 /* frame is too short */ |
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#define R_CR 0x00040000 /* CRC Error */ |
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#define R_OV 0x00020000 /* Overrun */ |
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#define R_CD 0x00010000 /* CD lost */ |
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#define R_CL 0x00010000 /* this frame is closed because of a |
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collision */ |
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/* Rx Data buffer must be 4 bytes aligned in most cases.*/ |
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#define UCC_SLOW_RX_ALIGN 4 |
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#define UCC_SLOW_MRBLR_ALIGNMENT 4 |
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#define UCC_SLOW_PRAM_SIZE 0x100 |
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#define ALIGNMENT_OF_UCC_SLOW_PRAM 64 |
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/* UCC Slow Channel Protocol Mode */ |
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enum ucc_slow_channel_protocol_mode { |
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UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002, |
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UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004, |
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UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008, |
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}; |
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/* UCC Slow Transparent Transmit CRC (TCRC) */ |
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enum ucc_slow_transparent_tcrc { |
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/* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */ |
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UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000, |
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/* CRC16 (BISYNC). (X16 + X15 + X2 + 1) */ |
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UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000, |
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/* 32-bit CCITT CRC (Ethernet and HDLC) */ |
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UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000, |
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}; |
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/* UCC Slow oversampling rate for transmitter (TDCR) */ |
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enum ucc_slow_tx_oversampling_rate { |
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/* 1x clock mode */ |
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UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000, |
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/* 8x clock mode */ |
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UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000, |
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/* 16x clock mode */ |
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UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000, |
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/* 32x clock mode */ |
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UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000, |
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}; |
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/* UCC Slow Oversampling rate for receiver (RDCR) |
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*/ |
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enum ucc_slow_rx_oversampling_rate { |
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/* 1x clock mode */ |
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UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000, |
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/* 8x clock mode */ |
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UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000, |
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/* 16x clock mode */ |
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UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000, |
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/* 32x clock mode */ |
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UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000, |
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}; |
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/* UCC Slow Transmitter encoding method (TENC) |
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*/ |
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enum ucc_slow_tx_encoding_method { |
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UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000, |
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UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100 |
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}; |
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/* UCC Slow Receiver decoding method (RENC) |
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*/ |
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enum ucc_slow_rx_decoding_method { |
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UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000, |
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UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800 |
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}; |
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/* UCC Slow Diagnostic mode (DIAG) |
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*/ |
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enum ucc_slow_diag_mode { |
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UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000, |
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UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040, |
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UCC_SLOW_DIAG_MODE_ECHO = 0x00000080, |
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UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0 |
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}; |
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struct ucc_slow_info { |
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int ucc_num; |
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int protocol; /* QE_CR_PROTOCOL_xxx */ |
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enum qe_clock rx_clock; |
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enum qe_clock tx_clock; |
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phys_addr_t regs; |
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int irq; |
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u16 uccm_mask; |
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int data_mem_part; |
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int init_tx; |
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int init_rx; |
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u32 tx_bd_ring_len; |
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u32 rx_bd_ring_len; |
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int rx_interrupts; |
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int brkpt_support; |
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int grant_support; |
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int tsa; |
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int cdp; |
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int cds; |
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int ctsp; |
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int ctss; |
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int rinv; |
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int tinv; |
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int rtsm; |
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int rfw; |
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int tci; |
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int tend; |
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int tfl; |
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int txsy; |
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u16 max_rx_buf_length; |
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enum ucc_slow_transparent_tcrc tcrc; |
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enum ucc_slow_channel_protocol_mode mode; |
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enum ucc_slow_diag_mode diag; |
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enum ucc_slow_tx_oversampling_rate tdcr; |
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enum ucc_slow_rx_oversampling_rate rdcr; |
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enum ucc_slow_tx_encoding_method tenc; |
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enum ucc_slow_rx_decoding_method renc; |
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}; |
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struct ucc_slow_private { |
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struct ucc_slow_info *us_info; |
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struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */ |
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struct ucc_slow_pram __iomem *us_pram; /* a pointer to the parameter RAM */ |
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s32 us_pram_offset; |
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int enabled_tx; /* Whether channel is enabled for Tx (ENT) */ |
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int enabled_rx; /* Whether channel is enabled for Rx (ENR) */ |
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int stopped_tx; /* Whether channel has been stopped for Tx |
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(STOP_TX, etc.) */ |
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int stopped_rx; /* Whether channel has been stopped for Rx */ |
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struct list_head confQ; /* frames passed to chip waiting for tx */ |
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u32 first_tx_bd_mask; /* mask is used in Tx routine to save status |
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and length for first BD in a frame */ |
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s32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */ |
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s32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */ |
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struct qe_bd __iomem *confBd; /* next BD for confirm after Tx */ |
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struct qe_bd __iomem *tx_bd; /* next BD for new Tx request */ |
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struct qe_bd __iomem *rx_bd; /* next BD to collect after Rx */ |
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void *p_rx_frame; /* accumulating receive frame */ |
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__be16 __iomem *p_ucce; /* a pointer to the event register in memory */ |
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__be16 __iomem *p_uccm; /* a pointer to the mask register in memory */ |
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u16 saved_uccm; /* a saved mask for the RX Interrupt bits */ |
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#ifdef STATISTICS |
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u32 tx_frames; /* Transmitted frames counters */ |
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u32 rx_frames; /* Received frames counters (only frames |
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passed to application) */ |
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u32 rx_discarded; /* Discarded frames counters (frames that |
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were discarded by the driver due to |
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errors) */ |
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#endif /* STATISTICS */ |
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}; |
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/* ucc_slow_init |
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* Initializes Slow UCC according to provided parameters. |
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* |
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* us_info - (In) pointer to the slow UCC info structure. |
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* uccs_ret - (Out) pointer to the slow UCC structure. |
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*/ |
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int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret); |
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/* ucc_slow_free |
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* Frees all resources for slow UCC. |
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* |
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* uccs - (In) pointer to the slow UCC structure. |
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*/ |
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void ucc_slow_free(struct ucc_slow_private * uccs); |
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/* ucc_slow_enable |
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* Enables a fast UCC port. |
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* This routine enables Tx and/or Rx through the General UCC Mode Register. |
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* |
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* uccs - (In) pointer to the slow UCC structure. |
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* mode - (In) TX, RX, or both. |
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*/ |
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void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode); |
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/* ucc_slow_disable |
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* Disables a fast UCC port. |
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* This routine disables Tx and/or Rx through the General UCC Mode Register. |
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* |
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* uccs - (In) pointer to the slow UCC structure. |
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* mode - (In) TX, RX, or both. |
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*/ |
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void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode); |
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/* ucc_slow_graceful_stop_tx |
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* Smoothly stops transmission on a specified slow UCC. |
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* |
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* uccs - (In) pointer to the slow UCC structure. |
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*/ |
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void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs); |
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/* ucc_slow_stop_tx |
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* Stops transmission on a specified slow UCC. |
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* |
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* uccs - (In) pointer to the slow UCC structure. |
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*/ |
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void ucc_slow_stop_tx(struct ucc_slow_private * uccs); |
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/* ucc_slow_restart_tx |
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* Restarts transmitting on a specified slow UCC. |
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* |
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* uccs - (In) pointer to the slow UCC structure. |
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*/ |
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void ucc_slow_restart_tx(struct ucc_slow_private *uccs); |
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u32 ucc_slow_get_qe_cr_subblock(int uccs_num); |
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#endif /* __UCC_SLOW_H__ */
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