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169 lines
5.5 KiB
169 lines
5.5 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* OMAP GPMC Platform data |
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* |
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* Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com |
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* Roger Quadros <[email protected]> |
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*/ |
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#ifndef _GPMC_OMAP_H_ |
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#define _GPMC_OMAP_H_ |
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/* Maximum Number of Chip Selects */ |
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#define GPMC_CS_NUM 8 |
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/* bool type time settings */ |
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struct gpmc_bool_timings { |
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bool cycle2cyclediffcsen; |
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bool cycle2cyclesamecsen; |
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bool we_extra_delay; |
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bool oe_extra_delay; |
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bool adv_extra_delay; |
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bool cs_extra_delay; |
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bool time_para_granularity; |
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}; |
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/* |
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* Note that all values in this struct are in nanoseconds except sync_clk |
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* (which is in picoseconds), while the register values are in gpmc_fck cycles. |
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*/ |
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struct gpmc_timings { |
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/* Minimum clock period for synchronous mode (in picoseconds) */ |
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u32 sync_clk; |
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/* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ |
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u32 cs_on; /* Assertion time */ |
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u32 cs_rd_off; /* Read deassertion time */ |
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u32 cs_wr_off; /* Write deassertion time */ |
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/* ADV signal timings corresponding to GPMC_CONFIG3 */ |
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u32 adv_on; /* Assertion time */ |
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u32 adv_rd_off; /* Read deassertion time */ |
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u32 adv_wr_off; /* Write deassertion time */ |
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u32 adv_aad_mux_on; /* ADV assertion time for AAD */ |
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u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */ |
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u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */ |
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/* WE signals timings corresponding to GPMC_CONFIG4 */ |
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u32 we_on; /* WE assertion time */ |
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u32 we_off; /* WE deassertion time */ |
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/* OE signals timings corresponding to GPMC_CONFIG4 */ |
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u32 oe_on; /* OE assertion time */ |
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u32 oe_off; /* OE deassertion time */ |
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u32 oe_aad_mux_on; /* OE assertion time for AAD */ |
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u32 oe_aad_mux_off; /* OE deassertion time for AAD */ |
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/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ |
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u32 page_burst_access; /* Multiple access word delay */ |
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u32 access; /* Start-cycle to first data valid delay */ |
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u32 rd_cycle; /* Total read cycle time */ |
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u32 wr_cycle; /* Total write cycle time */ |
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u32 bus_turnaround; |
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u32 cycle2cycle_delay; |
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u32 wait_monitoring; |
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u32 clk_activation; |
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/* The following are only on OMAP3430 */ |
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u32 wr_access; /* WRACCESSTIME */ |
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u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */ |
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struct gpmc_bool_timings bool_timings; |
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}; |
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/* Device timings in picoseconds */ |
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struct gpmc_device_timings { |
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u32 t_ceasu; /* address setup to CS valid */ |
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u32 t_avdasu; /* address setup to ADV valid */ |
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/* XXX: try to combine t_avdp_r & t_avdp_w. Issue is |
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* of tusb using these timings even for sync whilst |
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* ideally for adv_rd/(wr)_off it should have considered |
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* t_avdh instead. This indirectly necessitates r/w |
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* variations of t_avdp as it is possible to have one |
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* sync & other async |
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*/ |
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u32 t_avdp_r; /* ADV low time (what about t_cer ?) */ |
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u32 t_avdp_w; |
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u32 t_aavdh; /* address hold time */ |
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u32 t_oeasu; /* address setup to OE valid */ |
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u32 t_aa; /* access time from ADV assertion */ |
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u32 t_iaa; /* initial access time */ |
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u32 t_oe; /* access time from OE assertion */ |
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u32 t_ce; /* access time from CS asertion */ |
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u32 t_rd_cycle; /* read cycle time */ |
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u32 t_cez_r; /* read CS deassertion to high Z */ |
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u32 t_cez_w; /* write CS deassertion to high Z */ |
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u32 t_oez; /* OE deassertion to high Z */ |
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u32 t_weasu; /* address setup to WE valid */ |
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u32 t_wpl; /* write assertion time */ |
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u32 t_wph; /* write deassertion time */ |
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u32 t_wr_cycle; /* write cycle time */ |
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u32 clk; |
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u32 t_bacc; /* burst access valid clock to output delay */ |
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u32 t_ces; /* CS setup time to clk */ |
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u32 t_avds; /* ADV setup time to clk */ |
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u32 t_avdh; /* ADV hold time from clk */ |
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u32 t_ach; /* address hold time from clk */ |
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u32 t_rdyo; /* clk to ready valid */ |
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u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */ |
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u32 t_ce_avd; /* CS on to ADV on delay */ |
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/* XXX: check the possibility of combining |
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* cyc_aavhd_oe & cyc_aavdh_we |
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*/ |
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u8 cyc_aavdh_oe;/* read address hold time in cycles */ |
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u8 cyc_aavdh_we;/* write address hold time in cycles */ |
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u8 cyc_oe; /* access time from OE assertion in cycles */ |
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u8 cyc_wpl; /* write deassertion time in cycles */ |
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u32 cyc_iaa; /* initial access time in cycles */ |
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/* extra delays */ |
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bool ce_xdelay; |
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bool avd_xdelay; |
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bool oe_xdelay; |
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bool we_xdelay; |
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}; |
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#define GPMC_BURST_4 4 /* 4 word burst */ |
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#define GPMC_BURST_8 8 /* 8 word burst */ |
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#define GPMC_BURST_16 16 /* 16 word burst */ |
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#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */ |
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#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */ |
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#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */ |
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#define GPMC_MUX_AD 2 /* Addr-Data multiplex */ |
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struct gpmc_settings { |
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bool burst_wrap; /* enables wrap bursting */ |
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bool burst_read; /* enables read page/burst mode */ |
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bool burst_write; /* enables write page/burst mode */ |
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bool device_nand; /* device is NAND */ |
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bool sync_read; /* enables synchronous reads */ |
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bool sync_write; /* enables synchronous writes */ |
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bool wait_on_read; /* monitor wait on reads */ |
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bool wait_on_write; /* monitor wait on writes */ |
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u32 burst_len; /* page/burst length */ |
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u32 device_width; /* device bus width (8 or 16 bit) */ |
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u32 mux_add_data; /* multiplex address & data */ |
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u32 wait_pin; /* wait-pin to be used */ |
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}; |
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/* Data for each chip select */ |
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struct gpmc_omap_cs_data { |
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bool valid; /* data is valid */ |
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bool is_nand; /* device within this CS is NAND */ |
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struct gpmc_settings *settings; |
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struct gpmc_device_timings *device_timings; |
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struct gpmc_timings *gpmc_timings; |
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struct platform_device *pdev; /* device within this CS region */ |
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unsigned int pdata_size; |
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}; |
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struct gpmc_omap_platform_data { |
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struct gpmc_omap_cs_data cs[GPMC_CS_NUM]; |
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}; |
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#endif /* _GPMC_OMAP_H */
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