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358 lines
9.8 KiB
358 lines
9.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __LINUX_OMAP_DMA_H |
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#define __LINUX_OMAP_DMA_H |
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/* |
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* Legacy OMAP DMA handling defines and functions |
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* |
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* NOTE: Do not use these any longer. |
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* |
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* Use the generic dmaengine functions as defined in |
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* include/linux/dmaengine.h. |
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* |
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* Copyright (C) 2003 Nokia Corporation |
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* Author: Juha Yrjölä <[email protected]> |
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* |
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*/ |
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#include <linux/platform_device.h> |
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#define INT_DMA_LCD (NR_IRQS_LEGACY + 25) |
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#define OMAP1_DMA_TOUT_IRQ (1 << 0) |
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#define OMAP_DMA_DROP_IRQ (1 << 1) |
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#define OMAP_DMA_HALF_IRQ (1 << 2) |
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#define OMAP_DMA_FRAME_IRQ (1 << 3) |
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#define OMAP_DMA_LAST_IRQ (1 << 4) |
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#define OMAP_DMA_BLOCK_IRQ (1 << 5) |
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#define OMAP1_DMA_SYNC_IRQ (1 << 6) |
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#define OMAP2_DMA_PKT_IRQ (1 << 7) |
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#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8) |
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#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9) |
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#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) |
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#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) |
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#define OMAP_DMA_CCR_EN (1 << 7) |
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#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9) |
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#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10) |
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#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24) |
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#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) |
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#define OMAP_DMA_DATA_TYPE_S8 0x00 |
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#define OMAP_DMA_DATA_TYPE_S16 0x01 |
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#define OMAP_DMA_DATA_TYPE_S32 0x02 |
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#define OMAP_DMA_SYNC_ELEMENT 0x00 |
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#define OMAP_DMA_SYNC_FRAME 0x01 |
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#define OMAP_DMA_SYNC_BLOCK 0x02 |
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#define OMAP_DMA_SYNC_PACKET 0x03 |
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#define OMAP_DMA_DST_SYNC_PREFETCH 0x02 |
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#define OMAP_DMA_SRC_SYNC 0x01 |
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#define OMAP_DMA_DST_SYNC 0x00 |
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#define OMAP_DMA_PORT_EMIFF 0x00 |
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#define OMAP_DMA_PORT_EMIFS 0x01 |
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#define OMAP_DMA_PORT_OCP_T1 0x02 |
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#define OMAP_DMA_PORT_TIPB 0x03 |
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#define OMAP_DMA_PORT_OCP_T2 0x04 |
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#define OMAP_DMA_PORT_MPUI 0x05 |
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#define OMAP_DMA_AMODE_CONSTANT 0x00 |
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#define OMAP_DMA_AMODE_POST_INC 0x01 |
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#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 |
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#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 |
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#define DMA_DEFAULT_FIFO_DEPTH 0x10 |
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#define DMA_DEFAULT_ARB_RATE 0x01 |
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/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */ |
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#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */ |
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#define DMA_THREAD_RESERVE_ONET (0x01 << 12) |
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#define DMA_THREAD_RESERVE_TWOT (0x02 << 12) |
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#define DMA_THREAD_RESERVE_THREET (0x03 << 12) |
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#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */ |
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#define DMA_THREAD_FIFO_75 (0x01 << 14) |
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#define DMA_THREAD_FIFO_25 (0x02 << 14) |
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#define DMA_THREAD_FIFO_50 (0x03 << 14) |
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/* DMA4_OCP_SYSCONFIG bits */ |
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#define DMA_SYSCONFIG_MIDLEMODE_MASK (3 << 12) |
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#define DMA_SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8) |
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#define DMA_SYSCONFIG_EMUFREE (1 << 5) |
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#define DMA_SYSCONFIG_SIDLEMODE_MASK (3 << 3) |
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#define DMA_SYSCONFIG_SOFTRESET (1 << 2) |
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#define DMA_SYSCONFIG_AUTOIDLE (1 << 0) |
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#define DMA_SYSCONFIG_MIDLEMODE(n) ((n) << 12) |
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#define DMA_SYSCONFIG_SIDLEMODE(n) ((n) << 3) |
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#define DMA_IDLEMODE_SMARTIDLE 0x2 |
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#define DMA_IDLEMODE_NO_IDLE 0x1 |
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#define DMA_IDLEMODE_FORCE_IDLE 0x0 |
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/* Chaining modes*/ |
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#ifndef CONFIG_ARCH_OMAP1 |
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#define OMAP_DMA_STATIC_CHAIN 0x1 |
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#define OMAP_DMA_DYNAMIC_CHAIN 0x2 |
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#define OMAP_DMA_CHAIN_ACTIVE 0x1 |
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#define OMAP_DMA_CHAIN_INACTIVE 0x0 |
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#endif |
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#define DMA_CH_PRIO_HIGH 0x1 |
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#define DMA_CH_PRIO_LOW 0x0 /* Def */ |
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/* Errata handling */ |
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#define IS_DMA_ERRATA(id) (errata & (id)) |
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#define SET_DMA_ERRATA(id) (errata |= (id)) |
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#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0) |
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#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1) |
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#define DMA_ERRATA_i378 BIT(0x2) |
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#define DMA_ERRATA_i541 BIT(0x3) |
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#define DMA_ERRATA_i88 BIT(0x4) |
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#define DMA_ERRATA_3_3 BIT(0x5) |
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#define DMA_ROMCODE_BUG BIT(0x6) |
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/* Attributes for OMAP DMA Contrller */ |
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#define DMA_LINKED_LCH BIT(0x0) |
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#define GLOBAL_PRIORITY BIT(0x1) |
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#define RESERVE_CHANNEL BIT(0x2) |
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#define IS_CSSA_32 BIT(0x3) |
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#define IS_CDSA_32 BIT(0x4) |
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#define IS_RW_PRIORITY BIT(0x5) |
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#define ENABLE_1510_MODE BIT(0x6) |
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#define SRC_PORT BIT(0x7) |
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#define DST_PORT BIT(0x8) |
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#define SRC_INDEX BIT(0x9) |
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#define DST_INDEX BIT(0xa) |
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#define IS_BURST_ONLY4 BIT(0xb) |
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#define CLEAR_CSR_ON_READ BIT(0xc) |
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#define IS_WORD_16 BIT(0xd) |
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#define ENABLE_16XX_MODE BIT(0xe) |
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#define HS_CHANNELS_RESERVED BIT(0xf) |
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/* Defines for DMA Capabilities */ |
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#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) |
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#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19) |
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#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20) |
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enum omap_reg_offsets { |
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GCR, GSCR, GRST1, HW_ID, |
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PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID, |
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PCHD_ID, CAPS_0, CAPS_1, CAPS_2, |
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CAPS_3, CAPS_4, PCH2_SR, PCH0_SR, |
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PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0, |
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IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0, |
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IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS, |
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OCP_SYSCONFIG, |
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/* omap1+ specific */ |
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CPC, CCR2, LCH_CTRL, |
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/* Common registers for all omap's */ |
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CSDP, CCR, CICR, CSR, |
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CEN, CFN, CSFI, CSEI, |
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CSAC, CDAC, CDEI, |
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CDFI, CLNK_CTRL, |
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/* Channel specific registers */ |
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CSSA, CDSA, COLOR, |
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CCEN, CCFN, |
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/* omap3630 and omap4 specific */ |
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CDP, CNDP, CCDN, |
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}; |
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enum omap_dma_burst_mode { |
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OMAP_DMA_DATA_BURST_DIS = 0, |
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OMAP_DMA_DATA_BURST_4, |
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OMAP_DMA_DATA_BURST_8, |
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OMAP_DMA_DATA_BURST_16, |
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}; |
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enum end_type { |
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OMAP_DMA_LITTLE_ENDIAN = 0, |
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OMAP_DMA_BIG_ENDIAN |
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}; |
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enum omap_dma_color_mode { |
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OMAP_DMA_COLOR_DIS = 0, |
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OMAP_DMA_CONSTANT_FILL, |
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OMAP_DMA_TRANSPARENT_COPY |
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}; |
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enum omap_dma_write_mode { |
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OMAP_DMA_WRITE_NON_POSTED = 0, |
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OMAP_DMA_WRITE_POSTED, |
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OMAP_DMA_WRITE_LAST_NON_POSTED |
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}; |
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enum omap_dma_channel_mode { |
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OMAP_DMA_LCH_2D = 0, |
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OMAP_DMA_LCH_G, |
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OMAP_DMA_LCH_P, |
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OMAP_DMA_LCH_PD |
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}; |
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struct omap_dma_channel_params { |
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int data_type; /* data type 8,16,32 */ |
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int elem_count; /* number of elements in a frame */ |
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int frame_count; /* number of frames in a element */ |
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int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ |
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int src_amode; /* constant, post increment, indexed, |
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double indexed */ |
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unsigned long src_start; /* source address : physical */ |
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int src_ei; /* source element index */ |
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int src_fi; /* source frame index */ |
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int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ |
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int dst_amode; /* constant, post increment, indexed, |
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double indexed */ |
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unsigned long dst_start; /* source address : physical */ |
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int dst_ei; /* source element index */ |
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int dst_fi; /* source frame index */ |
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int trigger; /* trigger attached if the channel is |
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synchronized */ |
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int sync_mode; /* sycn on element, frame , block or packet */ |
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int src_or_dst_synch; /* source synch(1) or destination synch(0) */ |
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int ie; /* interrupt enabled */ |
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unsigned char read_prio;/* read priority */ |
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unsigned char write_prio;/* write priority */ |
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#ifndef CONFIG_ARCH_OMAP1 |
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enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */ |
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#endif |
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}; |
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struct omap_dma_lch { |
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int next_lch; |
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int dev_id; |
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u16 saved_csr; |
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u16 enabled_irqs; |
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const char *dev_name; |
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void (*callback)(int lch, u16 ch_status, void *data); |
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void *data; |
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long flags; |
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int state; |
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int chain_id; |
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int status; |
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}; |
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struct omap_dma_dev_attr { |
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u32 dev_caps; |
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u16 lch_count; |
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u16 chan_count; |
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}; |
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enum { |
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OMAP_DMA_REG_NONE, |
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OMAP_DMA_REG_16BIT, |
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OMAP_DMA_REG_2X16BIT, |
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OMAP_DMA_REG_32BIT, |
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}; |
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struct omap_dma_reg { |
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u16 offset; |
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u8 stride; |
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u8 type; |
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}; |
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#define SDMA_FILTER_PARAM(hw_req) ((int[]) { (hw_req) }) |
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struct dma_slave_map; |
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/* System DMA platform data structure */ |
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struct omap_system_dma_plat_info { |
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const struct omap_dma_reg *reg_map; |
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unsigned channel_stride; |
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struct omap_dma_dev_attr *dma_attr; |
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u32 errata; |
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void (*show_dma_caps)(void); |
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void (*clear_lch_regs)(int lch); |
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void (*clear_dma)(int lch); |
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void (*dma_write)(u32 val, int reg, int lch); |
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u32 (*dma_read)(int reg, int lch); |
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const struct dma_slave_map *slave_map; |
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int slavecnt; |
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}; |
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#ifdef CONFIG_ARCH_OMAP2PLUS |
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#define dma_omap2plus() 1 |
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#else |
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#define dma_omap2plus() 0 |
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#endif |
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#define dma_omap1() (!dma_omap2plus()) |
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#define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE) |
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#define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE) |
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#define dma_omap15xx() __dma_omap15xx(d) |
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#define dma_omap16xx() __dma_omap16xx(d) |
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#if defined(CONFIG_ARCH_OMAP) |
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extern struct omap_system_dma_plat_info *omap_get_plat_info(void); |
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extern void omap_set_dma_priority(int lch, int dst_port, int priority); |
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extern int omap_request_dma(int dev_id, const char *dev_name, |
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void (*callback)(int lch, u16 ch_status, void *data), |
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void *data, int *dma_ch); |
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extern void omap_disable_dma_irq(int ch, u16 irq_bits); |
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extern void omap_free_dma(int ch); |
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extern void omap_start_dma(int lch); |
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extern void omap_stop_dma(int lch); |
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extern void omap_set_dma_transfer_params(int lch, int data_type, |
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int elem_count, int frame_count, |
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int sync_mode, |
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int dma_trigger, int src_or_dst_synch); |
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extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); |
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extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, |
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unsigned long src_start, |
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int src_ei, int src_fi); |
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extern void omap_set_dma_src_data_pack(int lch, int enable); |
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extern void omap_set_dma_src_burst_mode(int lch, |
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enum omap_dma_burst_mode burst_mode); |
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extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, |
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unsigned long dest_start, |
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int dst_ei, int dst_fi); |
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extern void omap_set_dma_dest_data_pack(int lch, int enable); |
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extern void omap_set_dma_dest_burst_mode(int lch, |
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enum omap_dma_burst_mode burst_mode); |
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extern dma_addr_t omap_get_dma_src_pos(int lch); |
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extern dma_addr_t omap_get_dma_dst_pos(int lch); |
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extern int omap_get_dma_active_status(int lch); |
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extern int omap_dma_running(void); |
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#if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP) |
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#include <mach/lcd_dma.h> |
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#else |
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static inline int omap_lcd_dma_running(void) |
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{ |
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return 0; |
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} |
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#endif |
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#else /* CONFIG_ARCH_OMAP */ |
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static inline struct omap_system_dma_plat_info *omap_get_plat_info(void) |
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{ |
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return NULL; |
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} |
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static inline int omap_request_dma(int dev_id, const char *dev_name, |
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void (*callback)(int lch, u16 ch_status, void *data), |
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void *data, int *dma_ch) |
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{ |
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return -ENODEV; |
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} |
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static inline void omap_free_dma(int ch) { } |
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#endif /* CONFIG_ARCH_OMAP */ |
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#endif /* __LINUX_OMAP_DMA_H */
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