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74 lines
2.9 KiB
74 lines
2.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright Intel Corporation (C) 2014-2016. All Rights Reserved |
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* |
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* Declarations for Altera Arria10 MAX5 System Resource Chip |
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* |
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* Adapted from DA9052 |
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*/ |
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#ifndef __MFD_ALTERA_A10SR_H |
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#define __MFD_ALTERA_A10SR_H |
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#include <linux/completion.h> |
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#include <linux/list.h> |
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#include <linux/mfd/core.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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/* Write registers are always on even addresses */ |
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#define WRITE_REG_MASK 0xFE |
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/* Odd registers are always on odd addresses */ |
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#define READ_REG_MASK 0x01 |
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#define ALTR_A10SR_BITS_PER_REGISTER 8 |
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/* |
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* To find the correct register, we divide the input GPIO by |
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* the number of GPIO in each register. We then need to multiply |
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* by 2 because the reads are at odd addresses. |
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*/ |
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#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1) |
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#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER) |
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#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y)) |
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#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X)) |
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/* Arria10 System Controller Register Defines */ |
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#define ALTR_A10SR_NOP 0x00 /* No Change */ |
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#define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */ |
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#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */ |
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/* LED register Bit Definitions */ |
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#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */ |
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#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT |
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#define ALTR_A10SR_OUT_VALID_RANGE_HI 7 |
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#define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */ |
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#define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */ |
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/* Pushbutton & DIP Switch Bit Definitions */ |
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#define ALTR_A10SR_IN_VALID_RANGE_LO 8 |
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#define ALTR_A10SR_IN_VALID_RANGE_HI 15 |
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#define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */ |
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#define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */ |
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#define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */ |
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#define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */ |
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#define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */ |
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#define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */ |
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#define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */ |
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#define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */ |
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#define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */ |
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#define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */ |
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#define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */ |
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#define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */ |
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/** |
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* struct altr_a10sr - Altera Max5 MFD device private data structure |
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* @dev: : this device |
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* @regmap: the regmap assigned to the parent device. |
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*/ |
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struct altr_a10sr { |
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struct device *dev; |
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struct regmap *regmap; |
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}; |
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#endif /* __MFD_ALTERA_A10SR_H */
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