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54 lines
1.5 KiB
54 lines
1.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* This header provides clock numbers for the ingenic,x1000-cgu DT binding. |
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* |
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* They are roughly ordered as: |
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* - external clocks |
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* - PLLs |
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* - muxes/dividers in the order they appear in the x1000 programmers manual |
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* - gates in order of their bit in the CLKGR* registers |
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*/ |
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#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ |
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#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ |
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#define X1000_CLK_EXCLK 0 |
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#define X1000_CLK_RTCLK 1 |
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#define X1000_CLK_APLL 2 |
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#define X1000_CLK_MPLL 3 |
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#define X1000_CLK_OTGPHY 4 |
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#define X1000_CLK_SCLKA 5 |
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#define X1000_CLK_CPUMUX 6 |
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#define X1000_CLK_CPU 7 |
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#define X1000_CLK_L2CACHE 8 |
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#define X1000_CLK_AHB0 9 |
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#define X1000_CLK_AHB2PMUX 10 |
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#define X1000_CLK_AHB2 11 |
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#define X1000_CLK_PCLK 12 |
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#define X1000_CLK_DDR 13 |
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#define X1000_CLK_MAC 14 |
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#define X1000_CLK_LCD 15 |
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#define X1000_CLK_MSCMUX 16 |
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#define X1000_CLK_MSC0 17 |
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#define X1000_CLK_MSC1 18 |
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#define X1000_CLK_OTG 19 |
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#define X1000_CLK_SSIPLL 20 |
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#define X1000_CLK_SSIPLL_DIV2 21 |
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#define X1000_CLK_SSIMUX 22 |
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#define X1000_CLK_EMC 23 |
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#define X1000_CLK_EFUSE 24 |
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#define X1000_CLK_SFC 25 |
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#define X1000_CLK_I2C0 26 |
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#define X1000_CLK_I2C1 27 |
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#define X1000_CLK_I2C2 28 |
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#define X1000_CLK_UART0 29 |
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#define X1000_CLK_UART1 30 |
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#define X1000_CLK_UART2 31 |
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#define X1000_CLK_TCU 32 |
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#define X1000_CLK_SSI 33 |
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#define X1000_CLK_OST 34 |
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#define X1000_CLK_PDMA 35 |
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#define X1000_CLK_EXCLK_DIV512 36 |
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#define X1000_CLK_RTC 37 |
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#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
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