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610 lines
16 KiB
610 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Octeon Watchdog driver |
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* |
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* Copyright (C) 2007-2017 Cavium, Inc. |
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* |
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* Converted to use WATCHDOG_CORE by Aaro Koskinen <[email protected]>. |
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* |
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* Some parts derived from wdt.c |
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* |
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* (c) Copyright 1996-1997 Alan Cox <[email protected]>, |
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* All Rights Reserved. |
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* |
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* Neither Alan Cox nor CymruNet Ltd. admit liability nor provide |
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* warranty for any of this software. This material is provided |
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* "AS-IS" and at no charge. |
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* |
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* (c) Copyright 1995 Alan Cox <[email protected]> |
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* |
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* The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. |
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* For most systems this is less than 10 seconds, so to allow for |
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* software to request longer watchdog heartbeats, we maintain software |
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* counters to count multiples of the base rate. If the system locks |
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* up in such a manner that we can not run the software counters, the |
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* only result is a watchdog reset sooner than was requested. But |
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* that is OK, because in this case userspace would likely not be able |
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* to do anything anyhow. |
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* |
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* The hardware watchdog interval we call the period. The OCTEON |
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* watchdog goes through several stages, after the first period an |
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* irq is asserted, then if it is not reset, after the next period NMI |
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* is asserted, then after an additional period a chip wide soft reset. |
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* So for the software counters, we reset watchdog after each period |
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* and decrement the counter. But for the last two periods we need to |
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* let the watchdog progress to the NMI stage so we disable the irq |
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* and let it proceed. Once in the NMI, we print the register state |
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* to the serial port and then wait for the reset. |
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* |
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* A watchdog is maintained for each CPU in the system, that way if |
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* one CPU suffers a lockup, we also get a register dump and reset. |
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* The userspace ping resets the watchdog on all CPUs. |
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* |
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* Before userspace opens the watchdog device, we still run the |
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* watchdogs to catch any lockups that may be kernel related. |
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* |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/interrupt.h> |
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#include <linux/watchdog.h> |
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#include <linux/cpumask.h> |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/cpu.h> |
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#include <linux/irq.h> |
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#include <asm/mipsregs.h> |
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#include <asm/uasm.h> |
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#include <asm/octeon/octeon.h> |
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#include <asm/octeon/cvmx-boot-vector.h> |
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#include <asm/octeon/cvmx-ciu2-defs.h> |
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#include <asm/octeon/cvmx-rst-defs.h> |
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/* Watchdog interrupt major block number (8 MSBs of intsn) */ |
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#define WD_BLOCK_NUMBER 0x01 |
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static int divisor; |
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/* The count needed to achieve timeout_sec. */ |
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static unsigned int timeout_cnt; |
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/* The maximum period supported. */ |
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static unsigned int max_timeout_sec; |
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/* The current period. */ |
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static unsigned int timeout_sec; |
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/* Set to non-zero when userspace countdown mode active */ |
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static bool do_countdown; |
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static unsigned int countdown_reset; |
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static unsigned int per_cpu_countdown[NR_CPUS]; |
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static cpumask_t irq_enabled_cpus; |
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#define WD_TIMO 60 /* Default heartbeat = 60 seconds */ |
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#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull) |
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static int heartbeat = WD_TIMO; |
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module_param(heartbeat, int, 0444); |
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MODULE_PARM_DESC(heartbeat, |
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"Watchdog heartbeat in seconds. (0 < heartbeat, default=" |
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__MODULE_STRING(WD_TIMO) ")"); |
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static bool nowayout = WATCHDOG_NOWAYOUT; |
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module_param(nowayout, bool, 0444); |
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MODULE_PARM_DESC(nowayout, |
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"Watchdog cannot be stopped once started (default=" |
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
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static int disable; |
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module_param(disable, int, 0444); |
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MODULE_PARM_DESC(disable, |
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"Disable the watchdog entirely (default=0)"); |
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static struct cvmx_boot_vector_element *octeon_wdt_bootvector; |
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void octeon_wdt_nmi_stage2(void); |
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static int cpu2core(int cpu) |
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{ |
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#ifdef CONFIG_SMP |
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return cpu_logical_map(cpu) & 0x3f; |
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#else |
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return cvmx_get_core_num(); |
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#endif |
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} |
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/** |
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* Poke the watchdog when an interrupt is received |
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* |
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* @cpl: |
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* @dev_id: |
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* |
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* Returns |
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*/ |
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static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) |
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{ |
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int cpu = raw_smp_processor_id(); |
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unsigned int core = cpu2core(cpu); |
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int node = cpu_to_node(cpu); |
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if (do_countdown) { |
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if (per_cpu_countdown[cpu] > 0) { |
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/* We're alive, poke the watchdog */ |
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cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); |
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per_cpu_countdown[cpu]--; |
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} else { |
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/* Bad news, you are about to reboot. */ |
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disable_irq_nosync(cpl); |
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cpumask_clear_cpu(cpu, &irq_enabled_cpus); |
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} |
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} else { |
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/* Not open, just ping away... */ |
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cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); |
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} |
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return IRQ_HANDLED; |
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} |
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/* From setup.c */ |
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extern int prom_putchar(char c); |
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/** |
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* Write a string to the uart |
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* |
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* @str: String to write |
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*/ |
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static void octeon_wdt_write_string(const char *str) |
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{ |
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/* Just loop writing one byte at a time */ |
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while (*str) |
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prom_putchar(*str++); |
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} |
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/** |
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* Write a hex number out of the uart |
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* |
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* @value: Number to display |
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* @digits: Number of digits to print (1 to 16) |
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*/ |
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static void octeon_wdt_write_hex(u64 value, int digits) |
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{ |
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int d; |
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int v; |
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for (d = 0; d < digits; d++) { |
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v = (value >> ((digits - d - 1) * 4)) & 0xf; |
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if (v >= 10) |
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prom_putchar('a' + v - 10); |
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else |
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prom_putchar('0' + v); |
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} |
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} |
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static const char reg_name[][3] = { |
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"$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
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"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", |
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
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"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" |
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}; |
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/** |
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* NMI stage 3 handler. NMIs are handled in the following manner: |
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* 1) The first NMI handler enables CVMSEG and transfers from |
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* the bootbus region into normal memory. It is careful to not |
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* destroy any registers. |
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* 2) The second stage handler uses CVMSEG to save the registers |
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* and create a stack for C code. It then calls the third level |
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* handler with one argument, a pointer to the register values. |
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* 3) The third, and final, level handler is the following C |
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* function that prints out some useful infomration. |
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* |
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* @reg: Pointer to register state before the NMI |
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*/ |
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void octeon_wdt_nmi_stage3(u64 reg[32]) |
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{ |
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u64 i; |
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unsigned int coreid = cvmx_get_core_num(); |
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/* |
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* Save status and cause early to get them before any changes |
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* might happen. |
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*/ |
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u64 cp0_cause = read_c0_cause(); |
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u64 cp0_status = read_c0_status(); |
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u64 cp0_error_epc = read_c0_errorepc(); |
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u64 cp0_epc = read_c0_epc(); |
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/* Delay so output from all cores output is not jumbled together. */ |
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udelay(85000 * coreid); |
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octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); |
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octeon_wdt_write_hex(coreid, 2); |
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octeon_wdt_write_string(" ***\r\n"); |
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for (i = 0; i < 32; i++) { |
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octeon_wdt_write_string("\t"); |
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octeon_wdt_write_string(reg_name[i]); |
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octeon_wdt_write_string("\t0x"); |
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octeon_wdt_write_hex(reg[i], 16); |
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if (i & 1) |
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octeon_wdt_write_string("\r\n"); |
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} |
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octeon_wdt_write_string("\terr_epc\t0x"); |
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octeon_wdt_write_hex(cp0_error_epc, 16); |
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octeon_wdt_write_string("\tepc\t0x"); |
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octeon_wdt_write_hex(cp0_epc, 16); |
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octeon_wdt_write_string("\r\n"); |
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octeon_wdt_write_string("\tstatus\t0x"); |
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octeon_wdt_write_hex(cp0_status, 16); |
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octeon_wdt_write_string("\tcause\t0x"); |
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octeon_wdt_write_hex(cp0_cause, 16); |
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octeon_wdt_write_string("\r\n"); |
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/* The CIU register is different for each Octeon model. */ |
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if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { |
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octeon_wdt_write_string("\tsrc_wd\t0x"); |
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16); |
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octeon_wdt_write_string("\ten_wd\t0x"); |
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16); |
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octeon_wdt_write_string("\r\n"); |
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octeon_wdt_write_string("\tsrc_rml\t0x"); |
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16); |
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octeon_wdt_write_string("\ten_rml\t0x"); |
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16); |
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octeon_wdt_write_string("\r\n"); |
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octeon_wdt_write_string("\tsum\t0x"); |
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16); |
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octeon_wdt_write_string("\r\n"); |
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} else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) { |
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octeon_wdt_write_string("\tsum0\t0x"); |
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); |
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octeon_wdt_write_string("\ten0\t0x"); |
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); |
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octeon_wdt_write_string("\r\n"); |
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} |
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octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); |
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/* |
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* G-30204: We must trigger a soft reset before watchdog |
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* does an incomplete job of doing it. |
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*/ |
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if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) { |
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u64 scr; |
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unsigned int node = cvmx_get_node_num(); |
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unsigned int lcore = cvmx_get_local_core_num(); |
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union cvmx_ciu_wdogx ciu_wdog; |
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/* |
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* Wait for other cores to print out information, but |
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* not too long. Do the soft reset before watchdog |
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* can trigger it. |
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*/ |
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do { |
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ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore)); |
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} while (ciu_wdog.s.cnt > 0x10000); |
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scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0)); |
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scr |= 1 << 11; /* Indicate watchdog in bit 11 */ |
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cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr); |
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cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1); |
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} |
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} |
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static int octeon_wdt_cpu_to_irq(int cpu) |
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{ |
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unsigned int coreid; |
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int node; |
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int irq; |
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coreid = cpu2core(cpu); |
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node = cpu_to_node(cpu); |
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if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { |
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struct irq_domain *domain; |
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int hwirq; |
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domain = octeon_irq_get_block_domain(node, |
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WD_BLOCK_NUMBER); |
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hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid; |
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irq = irq_find_mapping(domain, hwirq); |
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} else { |
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irq = OCTEON_IRQ_WDOG0 + coreid; |
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} |
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return irq; |
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} |
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static int octeon_wdt_cpu_pre_down(unsigned int cpu) |
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{ |
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unsigned int core; |
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int node; |
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union cvmx_ciu_wdogx ciu_wdog; |
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core = cpu2core(cpu); |
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node = cpu_to_node(cpu); |
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/* Poke the watchdog to clear out its state */ |
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cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); |
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/* Disable the hardware. */ |
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ciu_wdog.u64 = 0; |
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cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); |
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free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq); |
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return 0; |
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} |
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static int octeon_wdt_cpu_online(unsigned int cpu) |
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{ |
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unsigned int core; |
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unsigned int irq; |
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union cvmx_ciu_wdogx ciu_wdog; |
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int node; |
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struct irq_domain *domain; |
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int hwirq; |
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core = cpu2core(cpu); |
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node = cpu_to_node(cpu); |
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octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2; |
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/* Disable it before doing anything with the interrupts. */ |
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ciu_wdog.u64 = 0; |
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cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); |
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per_cpu_countdown[cpu] = countdown_reset; |
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if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { |
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/* Must get the domain for the watchdog block */ |
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domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER); |
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/* Get a irq for the wd intsn (hardware interrupt) */ |
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hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core; |
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irq = irq_create_mapping(domain, hwirq); |
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irqd_set_trigger_type(irq_get_irq_data(irq), |
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IRQ_TYPE_EDGE_RISING); |
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} else |
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irq = OCTEON_IRQ_WDOG0 + core; |
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if (request_irq(irq, octeon_wdt_poke_irq, |
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IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) |
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panic("octeon_wdt: Couldn't obtain irq %d", irq); |
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/* Must set the irq affinity here */ |
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if (octeon_has_feature(OCTEON_FEATURE_CIU3)) { |
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cpumask_t mask; |
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cpumask_clear(&mask); |
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cpumask_set_cpu(cpu, &mask); |
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irq_set_affinity(irq, &mask); |
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} |
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cpumask_set_cpu(cpu, &irq_enabled_cpus); |
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/* Poke the watchdog to clear out its state */ |
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cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1); |
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/* Finally enable the watchdog now that all handlers are installed */ |
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ciu_wdog.u64 = 0; |
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ciu_wdog.s.len = timeout_cnt; |
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ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ |
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cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64); |
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return 0; |
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} |
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static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog) |
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{ |
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int cpu; |
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int coreid; |
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int node; |
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if (disable) |
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return 0; |
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for_each_online_cpu(cpu) { |
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coreid = cpu2core(cpu); |
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node = cpu_to_node(cpu); |
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cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); |
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per_cpu_countdown[cpu] = countdown_reset; |
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if ((countdown_reset || !do_countdown) && |
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!cpumask_test_cpu(cpu, &irq_enabled_cpus)) { |
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/* We have to enable the irq */ |
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enable_irq(octeon_wdt_cpu_to_irq(cpu)); |
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cpumask_set_cpu(cpu, &irq_enabled_cpus); |
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} |
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} |
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return 0; |
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} |
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static void octeon_wdt_calc_parameters(int t) |
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{ |
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unsigned int periods; |
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timeout_sec = max_timeout_sec; |
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/* |
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* Find the largest interrupt period, that can evenly divide |
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* the requested heartbeat time. |
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*/ |
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while ((t % timeout_sec) != 0) |
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timeout_sec--; |
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periods = t / timeout_sec; |
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/* |
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* The last two periods are after the irq is disabled, and |
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* then to the nmi, so we subtract them off. |
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*/ |
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countdown_reset = periods > 2 ? periods - 2 : 0; |
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heartbeat = t; |
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timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8; |
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} |
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static int octeon_wdt_set_timeout(struct watchdog_device *wdog, |
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unsigned int t) |
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{ |
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int cpu; |
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int coreid; |
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union cvmx_ciu_wdogx ciu_wdog; |
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int node; |
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if (t <= 0) |
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return -1; |
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octeon_wdt_calc_parameters(t); |
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if (disable) |
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return 0; |
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for_each_online_cpu(cpu) { |
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coreid = cpu2core(cpu); |
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node = cpu_to_node(cpu); |
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cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); |
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ciu_wdog.u64 = 0; |
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ciu_wdog.s.len = timeout_cnt; |
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ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ |
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cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); |
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cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1); |
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} |
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octeon_wdt_ping(wdog); /* Get the irqs back on. */ |
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return 0; |
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} |
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static int octeon_wdt_start(struct watchdog_device *wdog) |
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{ |
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octeon_wdt_ping(wdog); |
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do_countdown = 1; |
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return 0; |
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} |
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static int octeon_wdt_stop(struct watchdog_device *wdog) |
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{ |
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do_countdown = 0; |
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octeon_wdt_ping(wdog); |
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return 0; |
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} |
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static const struct watchdog_info octeon_wdt_info = { |
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.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
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.identity = "OCTEON", |
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}; |
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static const struct watchdog_ops octeon_wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = octeon_wdt_start, |
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.stop = octeon_wdt_stop, |
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.ping = octeon_wdt_ping, |
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.set_timeout = octeon_wdt_set_timeout, |
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}; |
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static struct watchdog_device octeon_wdt = { |
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.info = &octeon_wdt_info, |
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.ops = &octeon_wdt_ops, |
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}; |
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static enum cpuhp_state octeon_wdt_online; |
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/** |
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* Module/ driver initialization. |
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* |
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* Returns Zero on success |
|
*/ |
|
static int __init octeon_wdt_init(void) |
|
{ |
|
int ret; |
|
|
|
octeon_wdt_bootvector = cvmx_boot_vector_get(); |
|
if (!octeon_wdt_bootvector) { |
|
pr_err("Error: Cannot allocate boot vector.\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
|
divisor = 0x200; |
|
else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) |
|
divisor = 0x400; |
|
else |
|
divisor = 0x100; |
|
|
|
/* |
|
* Watchdog time expiration length = The 16 bits of LEN |
|
* represent the most significant bits of a 24 bit decrementer |
|
* that decrements every divisor cycle. |
|
* |
|
* Try for a timeout of 5 sec, if that fails a smaller number |
|
* of even seconds, |
|
*/ |
|
max_timeout_sec = 6; |
|
do { |
|
max_timeout_sec--; |
|
timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8; |
|
} while (timeout_cnt > 65535); |
|
|
|
BUG_ON(timeout_cnt == 0); |
|
|
|
octeon_wdt_calc_parameters(heartbeat); |
|
|
|
pr_info("Initial granularity %d Sec\n", timeout_sec); |
|
|
|
octeon_wdt.timeout = timeout_sec; |
|
octeon_wdt.max_timeout = UINT_MAX; |
|
|
|
watchdog_set_nowayout(&octeon_wdt, nowayout); |
|
|
|
ret = watchdog_register_device(&octeon_wdt); |
|
if (ret) { |
|
pr_err("watchdog_register_device() failed: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
if (disable) { |
|
pr_notice("disabled\n"); |
|
return 0; |
|
} |
|
|
|
cpumask_clear(&irq_enabled_cpus); |
|
|
|
ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online", |
|
octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down); |
|
if (ret < 0) |
|
goto err; |
|
octeon_wdt_online = ret; |
|
return 0; |
|
err: |
|
cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); |
|
watchdog_unregister_device(&octeon_wdt); |
|
return ret; |
|
} |
|
|
|
/** |
|
* Module / driver shutdown |
|
*/ |
|
static void __exit octeon_wdt_cleanup(void) |
|
{ |
|
watchdog_unregister_device(&octeon_wdt); |
|
|
|
if (disable) |
|
return; |
|
|
|
cpuhp_remove_state(octeon_wdt_online); |
|
|
|
/* |
|
* Disable the boot-bus memory, the code it points to is soon |
|
* to go missing. |
|
*/ |
|
cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); |
|
} |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Cavium Inc. <[email protected]>"); |
|
MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver."); |
|
module_init(octeon_wdt_init); |
|
module_exit(octeon_wdt_cleanup);
|
|
|