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61 lines
2.1 KiB
61 lines
2.1 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* drivers/watchdog/at91sam9_wdt.h |
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* |
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* Copyright (C) 2007 Andrew Victor |
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* Copyright (C) 2007 Atmel Corporation. |
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* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries |
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* |
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* Watchdog Timer (WDT) - System peripherals regsters. |
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* Based on AT91SAM9261 datasheet revision D. |
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* Based on SAM9X60 datasheet. |
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* |
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*/ |
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#ifndef AT91_WDT_H |
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#define AT91_WDT_H |
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#include <linux/bits.h> |
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#define AT91_WDT_CR 0x00 /* Watchdog Control Register */ |
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#define AT91_WDT_WDRSTT BIT(0) /* Restart */ |
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#define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ |
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#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ |
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#define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ |
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#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) |
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#define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */ |
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#define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */ |
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#define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */ |
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#define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */ |
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#define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */ |
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#define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */ |
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#define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */ |
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#define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */ |
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#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) |
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#define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */ |
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#define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */ |
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#define AT91_WDT_SR 0x08 /* Watchdog Status Register */ |
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#define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */ |
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#define AT91_WDT_WDERR BIT(1) /* Watchdog Error */ |
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/* Watchdog Timer Value Register */ |
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#define AT91_SAM9X60_VR 0x08 |
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/* Watchdog Window Level Register */ |
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#define AT91_SAM9X60_WLR 0x0c |
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/* Watchdog Period Value */ |
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#define AT91_SAM9X60_COUNTER (0xfffUL << 0) |
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#define AT91_SAM9X60_SET_COUNTER(x) ((x) & AT91_SAM9X60_COUNTER) |
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/* Interrupt Enable Register */ |
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#define AT91_SAM9X60_IER 0x14 |
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/* Period Interrupt Enable */ |
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#define AT91_SAM9X60_PERINT BIT(0) |
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/* Interrupt Disable Register */ |
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#define AT91_SAM9X60_IDR 0x18 |
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/* Interrupt Status Register */ |
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#define AT91_SAM9X60_ISR 0x1c |
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#endif
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