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417 lines
12 KiB
417 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* drivers/usb/gadget/qe_udc.h |
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* |
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* Copyright (C) 2006-2008 Freescale Semiconductor, Inc. All rights reserved. |
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* |
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* Xiaobo Xie <[email protected]> |
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* Li Yang <[email protected]> |
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* |
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* Description: |
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* Freescale USB device/endpoint management registers |
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*/ |
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#ifndef __FSL_QE_UDC_H |
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#define __FSL_QE_UDC_H |
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/* SoC type */ |
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#define PORT_CPM 0 |
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#define PORT_QE 1 |
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#define USB_MAX_ENDPOINTS 4 |
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#define USB_MAX_PIPES USB_MAX_ENDPOINTS |
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#define USB_EP0_MAX_SIZE 64 |
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#define USB_MAX_CTRL_PAYLOAD 0x4000 |
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#define USB_BDRING_LEN 16 |
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#define USB_BDRING_LEN_RX 256 |
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#define USB_BDRING_LEN_TX 16 |
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#define MIN_EMPTY_BDS 128 |
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#define MAX_DATA_BDS 8 |
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#define USB_CRC_SIZE 2 |
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#define USB_DIR_BOTH 0x88 |
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#define R_BUF_MAXSIZE 0x800 |
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#define USB_EP_PARA_ALIGNMENT 32 |
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/* USB Mode Register bit define */ |
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#define USB_MODE_EN 0x01 |
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#define USB_MODE_HOST 0x02 |
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#define USB_MODE_TEST 0x04 |
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#define USB_MODE_SFTE 0x08 |
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#define USB_MODE_RESUME 0x40 |
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#define USB_MODE_LSS 0x80 |
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/* USB Slave Address Register Mask */ |
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#define USB_SLVADDR_MASK 0x7F |
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/* USB Endpoint register define */ |
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#define USB_EPNUM_MASK 0xF000 |
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#define USB_EPNUM_SHIFT 12 |
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#define USB_TRANS_MODE_SHIFT 8 |
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#define USB_TRANS_CTR 0x0000 |
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#define USB_TRANS_INT 0x0100 |
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#define USB_TRANS_BULK 0x0200 |
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#define USB_TRANS_ISO 0x0300 |
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#define USB_EP_MF 0x0020 |
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#define USB_EP_RTE 0x0010 |
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#define USB_THS_SHIFT 2 |
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#define USB_THS_MASK 0x000c |
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#define USB_THS_NORMAL 0x0 |
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#define USB_THS_IGNORE_IN 0x0004 |
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#define USB_THS_NACK 0x0008 |
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#define USB_THS_STALL 0x000c |
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#define USB_RHS_SHIFT 0 |
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#define USB_RHS_MASK 0x0003 |
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#define USB_RHS_NORMAL 0x0 |
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#define USB_RHS_IGNORE_OUT 0x0001 |
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#define USB_RHS_NACK 0x0002 |
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#define USB_RHS_STALL 0x0003 |
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#define USB_RTHS_MASK 0x000f |
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/* USB Command Register define */ |
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#define USB_CMD_STR_FIFO 0x80 |
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#define USB_CMD_FLUSH_FIFO 0x40 |
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#define USB_CMD_ISFT 0x20 |
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#define USB_CMD_DSFT 0x10 |
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#define USB_CMD_EP_MASK 0x03 |
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/* USB Event and Mask Register define */ |
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#define USB_E_MSF_MASK 0x0800 |
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#define USB_E_SFT_MASK 0x0400 |
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#define USB_E_RESET_MASK 0x0200 |
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#define USB_E_IDLE_MASK 0x0100 |
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#define USB_E_TXE4_MASK 0x0080 |
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#define USB_E_TXE3_MASK 0x0040 |
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#define USB_E_TXE2_MASK 0x0020 |
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#define USB_E_TXE1_MASK 0x0010 |
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#define USB_E_SOF_MASK 0x0008 |
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#define USB_E_BSY_MASK 0x0004 |
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#define USB_E_TXB_MASK 0x0002 |
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#define USB_E_RXB_MASK 0x0001 |
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#define USBER_ALL_CLEAR 0x0fff |
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#define USB_E_DEFAULT_DEVICE (USB_E_RESET_MASK | USB_E_TXE4_MASK | \ |
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USB_E_TXE3_MASK | USB_E_TXE2_MASK | \ |
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USB_E_TXE1_MASK | USB_E_BSY_MASK | \ |
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USB_E_TXB_MASK | USB_E_RXB_MASK) |
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#define USB_E_TXE_MASK (USB_E_TXE4_MASK | USB_E_TXE3_MASK|\ |
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USB_E_TXE2_MASK | USB_E_TXE1_MASK) |
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/* USB Status Register define */ |
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#define USB_IDLE_STATUS_MASK 0x01 |
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/* USB Start of Frame Timer */ |
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#define USB_USSFT_MASK 0x3FFF |
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/* USB Frame Number Register */ |
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#define USB_USFRN_MASK 0xFFFF |
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struct usb_device_para{ |
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u16 epptr[4]; |
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u32 rstate; |
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u32 rptr; |
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u16 frame_n; |
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u16 rbcnt; |
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u32 rtemp; |
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u32 rxusb_data; |
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u16 rxuptr; |
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u8 reso[2]; |
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u32 softbl; |
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u8 sofucrctemp; |
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}; |
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struct usb_ep_para{ |
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u16 rbase; |
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u16 tbase; |
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u8 rbmr; |
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u8 tbmr; |
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u16 mrblr; |
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u16 rbptr; |
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u16 tbptr; |
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u32 tstate; |
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u32 tptr; |
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u16 tcrc; |
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u16 tbcnt; |
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u32 ttemp; |
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u16 txusbu_ptr; |
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u8 reserve[2]; |
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}; |
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#define USB_BUSMODE_GBL 0x20 |
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#define USB_BUSMODE_BO_MASK 0x18 |
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#define USB_BUSMODE_BO_SHIFT 0x3 |
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#define USB_BUSMODE_BE 0x2 |
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#define USB_BUSMODE_CETM 0x04 |
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#define USB_BUSMODE_DTB 0x02 |
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/* Endpoint basic handle */ |
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#define ep_index(EP) ((EP)->ep.desc->bEndpointAddress & 0xF) |
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#define ep_maxpacket(EP) ((EP)->ep.maxpacket) |
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#define ep_is_in(EP) ((ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ |
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USB_DIR_IN) : ((EP)->ep.desc->bEndpointAddress \ |
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& USB_DIR_IN) == USB_DIR_IN) |
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/* ep0 transfer state */ |
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#define WAIT_FOR_SETUP 0 |
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#define DATA_STATE_XMIT 1 |
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#define DATA_STATE_NEED_ZLP 2 |
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#define WAIT_FOR_OUT_STATUS 3 |
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#define DATA_STATE_RECV 4 |
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/* ep tramsfer mode */ |
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#define USBP_TM_CTL 0 |
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#define USBP_TM_ISO 1 |
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#define USBP_TM_BULK 2 |
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#define USBP_TM_INT 3 |
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/*----------------------------------------------------------------------------- |
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USB RX And TX DATA Frame |
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-----------------------------------------------------------------------------*/ |
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struct qe_frame{ |
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u8 *data; |
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u32 len; |
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u32 status; |
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u32 info; |
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void *privdata; |
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struct list_head node; |
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}; |
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/* Frame structure, info field. */ |
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#define PID_DATA0 0x80000000 /* Data toggle zero */ |
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#define PID_DATA1 0x40000000 /* Data toggle one */ |
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#define PID_SETUP 0x20000000 /* setup bit */ |
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#define SETUP_STATUS 0x10000000 /* setup status bit */ |
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#define SETADDR_STATUS 0x08000000 /* setupup address status bit */ |
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#define NO_REQ 0x04000000 /* Frame without request */ |
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#define HOST_DATA 0x02000000 /* Host data frame */ |
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#define FIRST_PACKET_IN_FRAME 0x01000000 /* first packet in the frame */ |
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#define TOKEN_FRAME 0x00800000 /* Host token frame */ |
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#define ZLP 0x00400000 /* Zero length packet */ |
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#define IN_TOKEN_FRAME 0x00200000 /* In token package */ |
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#define OUT_TOKEN_FRAME 0x00100000 /* Out token package */ |
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#define SETUP_TOKEN_FRAME 0x00080000 /* Setup token package */ |
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#define STALL_FRAME 0x00040000 /* Stall handshake */ |
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#define NACK_FRAME 0x00020000 /* Nack handshake */ |
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#define NO_PID 0x00010000 /* No send PID */ |
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#define NO_CRC 0x00008000 /* No send CRC */ |
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#define HOST_COMMAND 0x00004000 /* Host command frame */ |
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/* Frame status field */ |
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/* Receive side */ |
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#define FRAME_OK 0x00000000 /* Frame transmitted or received OK */ |
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#define FRAME_ERROR 0x80000000 /* Error occurred on frame */ |
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#define START_FRAME_LOST 0x40000000 /* START_FRAME_LOST */ |
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#define END_FRAME_LOST 0x20000000 /* END_FRAME_LOST */ |
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#define RX_ER_NONOCT 0x10000000 /* Rx Non Octet Aligned Packet */ |
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#define RX_ER_BITSTUFF 0x08000000 /* Frame Aborted --Received packet |
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with bit stuff error */ |
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#define RX_ER_CRC 0x04000000 /* Received packet with CRC error */ |
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#define RX_ER_OVERUN 0x02000000 /* Over-run occurred on reception */ |
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#define RX_ER_PID 0x01000000 /* Wrong PID received */ |
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/* Tranmit side */ |
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#define TX_ER_NAK 0x00800000 /* Received NAK handshake */ |
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#define TX_ER_STALL 0x00400000 /* Received STALL handshake */ |
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#define TX_ER_TIMEOUT 0x00200000 /* Transmit time out */ |
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#define TX_ER_UNDERUN 0x00100000 /* Transmit underrun */ |
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#define FRAME_INPROGRESS 0x00080000 /* Frame is being transmitted */ |
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#define ER_DATA_UNDERUN 0x00040000 /* Frame is shorter then expected */ |
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#define ER_DATA_OVERUN 0x00020000 /* Frame is longer then expected */ |
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/* QE USB frame operation functions */ |
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#define frame_get_length(frm) (frm->len) |
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#define frame_set_length(frm, leng) (frm->len = leng) |
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#define frame_get_data(frm) (frm->data) |
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#define frame_set_data(frm, dat) (frm->data = dat) |
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#define frame_get_info(frm) (frm->info) |
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#define frame_set_info(frm, inf) (frm->info = inf) |
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#define frame_get_status(frm) (frm->status) |
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#define frame_set_status(frm, stat) (frm->status = stat) |
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#define frame_get_privdata(frm) (frm->privdata) |
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#define frame_set_privdata(frm, dat) (frm->privdata = dat) |
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static inline void qe_frame_clean(struct qe_frame *frm) |
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{ |
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frame_set_data(frm, NULL); |
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frame_set_length(frm, 0); |
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frame_set_status(frm, FRAME_OK); |
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frame_set_info(frm, 0); |
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frame_set_privdata(frm, NULL); |
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} |
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static inline void qe_frame_init(struct qe_frame *frm) |
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{ |
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qe_frame_clean(frm); |
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INIT_LIST_HEAD(&(frm->node)); |
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} |
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struct qe_req { |
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struct usb_request req; |
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struct list_head queue; |
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/* ep_queue() func will add |
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a request->queue into a udc_ep->queue 'd tail */ |
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struct qe_ep *ep; |
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unsigned mapped:1; |
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}; |
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struct qe_ep { |
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struct usb_ep ep; |
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struct list_head queue; |
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struct qe_udc *udc; |
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struct usb_gadget *gadget; |
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u8 state; |
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struct qe_bd __iomem *rxbase; |
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struct qe_bd __iomem *n_rxbd; |
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struct qe_bd __iomem *e_rxbd; |
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struct qe_bd __iomem *txbase; |
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struct qe_bd __iomem *n_txbd; |
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struct qe_bd __iomem *c_txbd; |
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struct qe_frame *rxframe; |
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u8 *rxbuffer; |
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dma_addr_t rxbuf_d; |
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u8 rxbufmap; |
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unsigned char localnack; |
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int has_data; |
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struct qe_frame *txframe; |
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struct qe_req *tx_req; |
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int sent; /*data already sent */ |
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int last; /*data sent in the last time*/ |
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u8 dir; |
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u8 epnum; |
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u8 tm; /* transfer mode */ |
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u8 data01; |
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u8 init; |
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u8 already_seen; |
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u8 enable_tasklet; |
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u8 setup_stage; |
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u32 last_io; /* timestamp */ |
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char name[14]; |
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unsigned double_buf:1; |
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unsigned stopped:1; |
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unsigned fnf:1; |
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unsigned has_dma:1; |
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u8 ackwait; |
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u8 dma_channel; |
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u16 dma_counter; |
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int lch; |
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struct timer_list timer; |
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}; |
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struct qe_udc { |
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struct usb_gadget gadget; |
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struct usb_gadget_driver *driver; |
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struct device *dev; |
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struct qe_ep eps[USB_MAX_ENDPOINTS]; |
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struct usb_ctrlrequest local_setup_buff; |
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spinlock_t lock; /* lock for set/config qe_udc */ |
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unsigned long soc_type; /* QE or CPM soc */ |
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struct qe_req *status_req; /* ep0 status request */ |
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/* USB and EP Parameter Block pointer */ |
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struct usb_device_para __iomem *usb_param; |
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struct usb_ep_para __iomem *ep_param[4]; |
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u32 max_pipes; /* Device max pipes */ |
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u32 max_use_endpts; /* Max endpointes to be used */ |
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u32 bus_reset; /* Device is bus reseting */ |
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u32 resume_state; /* USB state to resume*/ |
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u32 usb_state; /* USB current state */ |
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u32 usb_next_state; /* USB next state */ |
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u32 ep0_state; /* Endpoint zero state */ |
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u32 ep0_dir; /* Endpoint zero direction: can be |
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USB_DIR_IN or USB_DIR_OUT*/ |
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u32 usb_sof_count; /* SOF count */ |
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u32 errors; /* USB ERRORs count */ |
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u8 *tmpbuf; |
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u32 c_start; |
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u32 c_end; |
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u8 *nullbuf; |
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u8 *statusbuf; |
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dma_addr_t nullp; |
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u8 nullmap; |
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u8 device_address; /* Device USB address */ |
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unsigned int usb_clock; |
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unsigned int usb_irq; |
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struct usb_ctlr __iomem *usb_regs; |
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struct tasklet_struct rx_tasklet; |
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struct completion *done; /* to make sure release() is done */ |
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}; |
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#define EP_STATE_IDLE 0 |
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#define EP_STATE_NACK 1 |
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#define EP_STATE_STALL 2 |
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/* |
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* transmit BD's status |
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*/ |
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#define T_R 0x80000000 /* ready bit */ |
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#define T_W 0x20000000 /* wrap bit */ |
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#define T_I 0x10000000 /* interrupt on completion */ |
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#define T_L 0x08000000 /* last */ |
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#define T_TC 0x04000000 /* transmit CRC */ |
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#define T_CNF 0x02000000 /* wait for transmit confirm */ |
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#define T_LSP 0x01000000 /* Low-speed transaction */ |
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#define T_PID 0x00c00000 /* packet id */ |
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#define T_NAK 0x00100000 /* No ack. */ |
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#define T_STAL 0x00080000 /* Stall received */ |
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#define T_TO 0x00040000 /* time out */ |
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#define T_UN 0x00020000 /* underrun */ |
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#define DEVICE_T_ERROR (T_UN | T_TO) |
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#define HOST_T_ERROR (T_UN | T_TO | T_NAK | T_STAL) |
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#define DEVICE_T_BD_MASK DEVICE_T_ERROR |
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#define HOST_T_BD_MASK HOST_T_ERROR |
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#define T_PID_SHIFT 6 |
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#define T_PID_DATA0 0x00800000 /* Data 0 toggle */ |
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#define T_PID_DATA1 0x00c00000 /* Data 1 toggle */ |
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/* |
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* receive BD's status |
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*/ |
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#define R_E 0x80000000 /* buffer empty */ |
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#define R_W 0x20000000 /* wrap bit */ |
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#define R_I 0x10000000 /* interrupt on reception */ |
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#define R_L 0x08000000 /* last */ |
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#define R_F 0x04000000 /* first */ |
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#define R_PID 0x00c00000 /* packet id */ |
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#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */ |
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#define R_AB 0x00080000 /* Frame Aborted */ |
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#define R_CR 0x00040000 /* CRC Error */ |
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#define R_OV 0x00020000 /* Overrun */ |
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#define R_ERROR (R_NO | R_AB | R_CR | R_OV) |
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#define R_BD_MASK R_ERROR |
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#define R_PID_DATA0 0x00000000 |
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#define R_PID_DATA1 0x00400000 |
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#define R_PID_SETUP 0x00800000 |
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#define CPM_USB_STOP_TX 0x2e600000 |
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#define CPM_USB_RESTART_TX 0x2e600000 |
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#define CPM_USB_STOP_TX_OPCODE 0x0a |
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#define CPM_USB_RESTART_TX_OPCODE 0x0b |
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#define CPM_USB_EP_SHIFT 5 |
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#endif /* __FSL_QE_UDC_H */
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