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623 lines
16 KiB
623 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2020 Linaro Limited |
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* |
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* Based on original driver: |
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* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/iio/adc/qcom-vadc-common.h> |
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#include <linux/iio/consumer.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/thermal.h> |
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|
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/* |
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* Thermal monitoring block consists of 8 (ADC_TM5_NUM_CHANNELS) channels. Each |
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* channel is programmed to use one of ADC channels for voltage comparison. |
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* Voltages are programmed using ADC codes, so we have to convert temp to |
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* voltage and then to ADC code value. |
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* |
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* Configuration of TM channels must match configuration of corresponding ADC |
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* channels. |
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*/ |
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|
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#define ADC5_MAX_CHANNEL 0xc0 |
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#define ADC_TM5_NUM_CHANNELS 8 |
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|
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#define ADC_TM5_STATUS_LOW 0x0a |
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|
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#define ADC_TM5_STATUS_HIGH 0x0b |
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|
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#define ADC_TM5_NUM_BTM 0x0f |
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|
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#define ADC_TM5_ADC_DIG_PARAM 0x42 |
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|
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#define ADC_TM5_FAST_AVG_CTL (ADC_TM5_ADC_DIG_PARAM + 1) |
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#define ADC_TM5_FAST_AVG_EN BIT(7) |
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|
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#define ADC_TM5_MEAS_INTERVAL_CTL (ADC_TM5_ADC_DIG_PARAM + 2) |
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#define ADC_TM5_TIMER1 3 /* 3.9ms */ |
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|
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#define ADC_TM5_MEAS_INTERVAL_CTL2 (ADC_TM5_ADC_DIG_PARAM + 3) |
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#define ADC_TM5_MEAS_INTERVAL_CTL2_MASK 0xf0 |
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#define ADC_TM5_TIMER2 10 /* 1 second */ |
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#define ADC_TM5_MEAS_INTERVAL_CTL3_MASK 0xf |
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#define ADC_TM5_TIMER3 4 /* 4 second */ |
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|
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#define ADC_TM_EN_CTL1 0x46 |
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#define ADC_TM_EN BIT(7) |
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#define ADC_TM_CONV_REQ 0x47 |
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#define ADC_TM_CONV_REQ_EN BIT(7) |
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|
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#define ADC_TM5_M_CHAN_BASE 0x60 |
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|
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#define ADC_TM5_M_ADC_CH_SEL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0) |
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#define ADC_TM5_M_LOW_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1) |
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#define ADC_TM5_M_LOW_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2) |
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#define ADC_TM5_M_HIGH_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3) |
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#define ADC_TM5_M_HIGH_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4) |
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#define ADC_TM5_M_MEAS_INTERVAL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5) |
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#define ADC_TM5_M_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6) |
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#define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK 0xf |
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#define ADC_TM5_M_CTL_CAL_SEL_MASK 0x30 |
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#define ADC_TM5_M_CTL_CAL_VAL 0x40 |
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#define ADC_TM5_M_EN(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7) |
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#define ADC_TM5_M_MEAS_EN BIT(7) |
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#define ADC_TM5_M_HIGH_THR_INT_EN BIT(1) |
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#define ADC_TM5_M_LOW_THR_INT_EN BIT(0) |
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|
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enum adc5_timer_select { |
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ADC5_TIMER_SEL_1 = 0, |
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ADC5_TIMER_SEL_2, |
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ADC5_TIMER_SEL_3, |
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ADC5_TIMER_SEL_NONE, |
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}; |
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struct adc_tm5_data { |
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const u32 full_scale_code_volt; |
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unsigned int *decimation; |
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unsigned int *hw_settle; |
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}; |
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|
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enum adc_tm5_cal_method { |
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ADC_TM5_NO_CAL = 0, |
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ADC_TM5_RATIOMETRIC_CAL, |
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ADC_TM5_ABSOLUTE_CAL |
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}; |
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struct adc_tm5_chip; |
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|
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/** |
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* struct adc_tm5_channel - ADC Thermal Monitoring channel data. |
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* @channel: channel number. |
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* @adc_channel: corresponding ADC channel number. |
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* @cal_method: calibration method. |
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* @prescale: channel scaling performed on the input signal. |
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* @hw_settle_time: the time between AMUX being configured and the |
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* start of conversion. |
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* @iio: IIO channel instance used by this channel. |
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* @chip: ADC TM chip instance. |
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* @tzd: thermal zone device used by this channel. |
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*/ |
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struct adc_tm5_channel { |
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unsigned int channel; |
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unsigned int adc_channel; |
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enum adc_tm5_cal_method cal_method; |
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unsigned int prescale; |
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unsigned int hw_settle_time; |
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struct iio_channel *iio; |
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struct adc_tm5_chip *chip; |
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struct thermal_zone_device *tzd; |
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}; |
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/** |
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* struct adc_tm5_chip - ADC Thermal Monitoring properties |
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* @regmap: SPMI ADC5 Thermal Monitoring peripheral register map field. |
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* @dev: SPMI ADC5 device. |
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* @data: software configuration data. |
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* @channels: array of ADC TM channel data. |
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* @nchannels: amount of channels defined/allocated |
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* @decimation: sampling rate supported for the channel. |
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* @avg_samples: ability to provide single result from the ADC |
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* that is an average of multiple measurements. |
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* @base: base address of TM registers. |
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*/ |
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struct adc_tm5_chip { |
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struct regmap *regmap; |
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struct device *dev; |
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const struct adc_tm5_data *data; |
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struct adc_tm5_channel *channels; |
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unsigned int nchannels; |
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unsigned int decimation; |
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unsigned int avg_samples; |
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u16 base; |
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}; |
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static const struct adc_tm5_data adc_tm5_data_pmic = { |
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.full_scale_code_volt = 0x70e4, |
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.decimation = (unsigned int []) { 250, 420, 840 }, |
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.hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700, |
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1000, 2000, 4000, 8000, 16000, 32000, |
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64000, 128000 }, |
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}; |
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static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) |
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{ |
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return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len); |
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} |
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static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) |
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{ |
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return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len); |
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} |
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static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val) |
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{ |
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return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val); |
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} |
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static irqreturn_t adc_tm5_isr(int irq, void *data) |
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{ |
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struct adc_tm5_chip *chip = data; |
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u8 status_low, status_high, ctl; |
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int ret, i; |
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|
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ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, sizeof(status_low)); |
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if (unlikely(ret)) { |
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dev_err(chip->dev, "read status low failed: %d\n", ret); |
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return IRQ_HANDLED; |
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} |
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ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, sizeof(status_high)); |
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if (unlikely(ret)) { |
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dev_err(chip->dev, "read status high failed: %d\n", ret); |
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return IRQ_HANDLED; |
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} |
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for (i = 0; i < chip->nchannels; i++) { |
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bool upper_set = false, lower_set = false; |
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unsigned int ch = chip->channels[i].channel; |
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|
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/* No TZD, we warned at the boot time */ |
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if (!chip->channels[i].tzd) |
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continue; |
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ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, sizeof(ctl)); |
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if (unlikely(ret)) { |
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dev_err(chip->dev, "ctl read failed: %d, channel %d\n", ret, i); |
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continue; |
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} |
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if (!(ctl & ADC_TM5_M_MEAS_EN)) |
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continue; |
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lower_set = (status_low & BIT(ch)) && |
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(ctl & ADC_TM5_M_LOW_THR_INT_EN); |
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upper_set = (status_high & BIT(ch)) && |
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(ctl & ADC_TM5_M_HIGH_THR_INT_EN); |
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|
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if (upper_set || lower_set) |
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thermal_zone_device_update(chip->channels[i].tzd, |
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THERMAL_EVENT_UNSPECIFIED); |
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} |
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|
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return IRQ_HANDLED; |
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} |
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static int adc_tm5_get_temp(void *data, int *temp) |
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{ |
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struct adc_tm5_channel *channel = data; |
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int ret; |
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if (!channel || !channel->iio) |
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return -EINVAL; |
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ret = iio_read_channel_processed(channel->iio, temp); |
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if (ret < 0) |
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return ret; |
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if (ret != IIO_VAL_INT) |
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return -EINVAL; |
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return 0; |
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} |
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static int adc_tm5_disable_channel(struct adc_tm5_channel *channel) |
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{ |
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struct adc_tm5_chip *chip = channel->chip; |
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unsigned int reg = ADC_TM5_M_EN(channel->channel); |
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return adc_tm5_reg_update(chip, reg, |
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ADC_TM5_M_MEAS_EN | |
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ADC_TM5_M_HIGH_THR_INT_EN | |
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ADC_TM5_M_LOW_THR_INT_EN, |
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0); |
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} |
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static int adc_tm5_enable(struct adc_tm5_chip *chip) |
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{ |
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int ret; |
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u8 data; |
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data = ADC_TM_EN; |
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ret = adc_tm5_write(chip, ADC_TM_EN_CTL1, &data, sizeof(data)); |
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if (ret < 0) { |
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dev_err(chip->dev, "adc-tm enable failed\n"); |
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return ret; |
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} |
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data = ADC_TM_CONV_REQ_EN; |
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ret = adc_tm5_write(chip, ADC_TM_CONV_REQ, &data, sizeof(data)); |
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if (ret < 0) { |
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dev_err(chip->dev, "adc-tm request conversion failed\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int adc_tm5_configure(struct adc_tm5_channel *channel, int low, int high) |
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{ |
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struct adc_tm5_chip *chip = channel->chip; |
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u8 buf[8]; |
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u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel); |
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int ret; |
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ret = adc_tm5_read(chip, reg, buf, sizeof(buf)); |
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if (ret) { |
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dev_err(chip->dev, "channel %d params read failed: %d\n", channel->channel, ret); |
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return ret; |
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} |
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buf[0] = channel->adc_channel; |
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/* High temperature corresponds to low voltage threshold */ |
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if (high != INT_MAX) { |
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u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, |
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chip->data->full_scale_code_volt, high); |
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buf[1] = adc_code & 0xff; |
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buf[2] = adc_code >> 8; |
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buf[7] |= ADC_TM5_M_LOW_THR_INT_EN; |
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} else { |
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buf[7] &= ~ADC_TM5_M_LOW_THR_INT_EN; |
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} |
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/* Low temperature corresponds to high voltage threshold */ |
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if (low != -INT_MAX) { |
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u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, |
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chip->data->full_scale_code_volt, low); |
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buf[3] = adc_code & 0xff; |
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buf[4] = adc_code >> 8; |
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buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN; |
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} else { |
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buf[7] &= ~ADC_TM5_M_HIGH_THR_INT_EN; |
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} |
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buf[5] = ADC5_TIMER_SEL_2; |
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/* Set calibration select, hw_settle delay */ |
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buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK; |
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buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time); |
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buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK; |
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buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method); |
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buf[7] |= ADC_TM5_M_MEAS_EN; |
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ret = adc_tm5_write(chip, reg, buf, sizeof(buf)); |
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if (ret) { |
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dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret); |
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return ret; |
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} |
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return adc_tm5_enable(chip); |
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} |
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static int adc_tm5_set_trips(void *data, int low, int high) |
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{ |
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struct adc_tm5_channel *channel = data; |
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struct adc_tm5_chip *chip; |
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int ret; |
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if (!channel) |
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return -EINVAL; |
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chip = channel->chip; |
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dev_dbg(chip->dev, "%d:low(mdegC):%d, high(mdegC):%d\n", |
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channel->channel, low, high); |
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|
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if (high == INT_MAX && low <= -INT_MAX) |
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ret = adc_tm5_disable_channel(channel); |
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else |
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ret = adc_tm5_configure(channel, low, high); |
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return ret; |
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} |
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static struct thermal_zone_of_device_ops adc_tm5_ops = { |
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.get_temp = adc_tm5_get_temp, |
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.set_trips = adc_tm5_set_trips, |
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}; |
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static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm) |
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{ |
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unsigned int i; |
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struct thermal_zone_device *tzd; |
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for (i = 0; i < adc_tm->nchannels; i++) { |
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adc_tm->channels[i].chip = adc_tm; |
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tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev, |
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adc_tm->channels[i].channel, |
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&adc_tm->channels[i], |
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&adc_tm5_ops); |
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if (IS_ERR(tzd)) { |
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dev_err(adc_tm->dev, "Error registering TZ zone for channel %d: %ld\n", |
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adc_tm->channels[i].channel, PTR_ERR(tzd)); |
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return PTR_ERR(tzd); |
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} |
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adc_tm->channels[i].tzd = tzd; |
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} |
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return 0; |
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} |
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static int adc_tm5_init(struct adc_tm5_chip *chip) |
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{ |
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u8 buf[4], channels_available; |
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int ret; |
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unsigned int i; |
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|
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ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM, |
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&channels_available, sizeof(channels_available)); |
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if (ret) { |
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dev_err(chip->dev, "read failed for BTM channels\n"); |
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return ret; |
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} |
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|
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for (i = 0; i < chip->nchannels; i++) { |
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if (chip->channels[i].channel >= channels_available) { |
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dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); |
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return -EINVAL; |
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} |
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} |
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buf[0] = chip->decimation; |
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buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; |
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buf[2] = ADC_TM5_TIMER1; |
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buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) | |
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FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3); |
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ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf)); |
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if (ret) { |
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dev_err(chip->dev, "block write failed: %d\n", ret); |
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return ret; |
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} |
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|
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return ret; |
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} |
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|
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static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm, |
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struct adc_tm5_channel *channel, |
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struct device_node *node) |
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{ |
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const char *name = node->name; |
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u32 chan, value, varr[2]; |
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int ret; |
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struct device *dev = adc_tm->dev; |
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struct of_phandle_args args; |
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|
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ret = of_property_read_u32(node, "reg", &chan); |
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if (ret) { |
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dev_err(dev, "%s: invalid channel number %d\n", name, ret); |
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return ret; |
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} |
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|
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if (chan >= ADC_TM5_NUM_CHANNELS) { |
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dev_err(dev, "%s: channel number too big: %d\n", name, chan); |
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return -EINVAL; |
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} |
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|
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channel->channel = chan; |
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|
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/* |
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* We are tied to PMIC's ADC controller, which always use single |
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* argument for channel number. So don't bother parsing |
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* #io-channel-cells, just enforce cell_count = 1. |
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*/ |
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ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args); |
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if (ret < 0) { |
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dev_err(dev, "%s: error parsing ADC channel number %d: %d\n", name, chan, ret); |
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return ret; |
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} |
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of_node_put(args.np); |
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|
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if (args.args_count != 1 || args.args[0] >= ADC5_MAX_CHANNEL) { |
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dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan); |
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return ret; |
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} |
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channel->adc_channel = args.args[0]; |
|
|
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channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, NULL); |
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if (IS_ERR(channel->iio)) { |
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ret = PTR_ERR(channel->iio); |
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if (ret != -EPROBE_DEFER) |
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dev_err(dev, "%s: error getting channel: %d\n", name, ret); |
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return ret; |
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} |
|
|
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ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); |
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if (!ret) { |
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ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); |
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if (ret < 0) { |
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dev_err(dev, "%s: invalid pre-scaling <%d %d>\n", |
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name, varr[0], varr[1]); |
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return ret; |
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} |
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channel->prescale = ret; |
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} else { |
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/* 1:1 prescale is index 0 */ |
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channel->prescale = 0; |
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} |
|
|
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ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value); |
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if (!ret) { |
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ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle); |
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if (ret < 0) { |
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dev_err(dev, "%s invalid hw-settle-time-us %d us\n", |
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name, value); |
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return ret; |
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} |
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channel->hw_settle_time = ret; |
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} else { |
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channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; |
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} |
|
|
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if (of_property_read_bool(node, "qcom,ratiometric")) |
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channel->cal_method = ADC_TM5_RATIOMETRIC_CAL; |
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else |
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channel->cal_method = ADC_TM5_ABSOLUTE_CAL; |
|
|
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return 0; |
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} |
|
|
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static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node) |
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{ |
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struct adc_tm5_channel *channels; |
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struct device_node *child; |
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u32 value; |
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int ret; |
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struct device *dev = adc_tm->dev; |
|
|
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adc_tm->nchannels = of_get_available_child_count(node); |
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if (!adc_tm->nchannels) |
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return -EINVAL; |
|
|
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adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels, |
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sizeof(*adc_tm->channels), GFP_KERNEL); |
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if (!adc_tm->channels) |
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return -ENOMEM; |
|
|
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channels = adc_tm->channels; |
|
|
|
adc_tm->data = of_device_get_match_data(dev); |
|
if (!adc_tm->data) |
|
adc_tm->data = &adc_tm5_data_pmic; |
|
|
|
ret = of_property_read_u32(node, "qcom,decimation", &value); |
|
if (!ret) { |
|
ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation); |
|
if (ret < 0) { |
|
dev_err(dev, "invalid decimation %d\n", value); |
|
return ret; |
|
} |
|
adc_tm->decimation = ret; |
|
} else { |
|
adc_tm->decimation = ADC5_DECIMATION_DEFAULT; |
|
} |
|
|
|
ret = of_property_read_u32(node, "qcom,avg-samples", &value); |
|
if (!ret) { |
|
ret = qcom_adc5_avg_samples_from_dt(value); |
|
if (ret < 0) { |
|
dev_err(dev, "invalid avg-samples %d\n", value); |
|
return ret; |
|
} |
|
adc_tm->avg_samples = ret; |
|
} else { |
|
adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES; |
|
} |
|
|
|
for_each_available_child_of_node(node, child) { |
|
ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child); |
|
if (ret) { |
|
of_node_put(child); |
|
return ret; |
|
} |
|
|
|
channels++; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int adc_tm5_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *node = pdev->dev.of_node; |
|
struct device *dev = &pdev->dev; |
|
struct adc_tm5_chip *adc_tm; |
|
struct regmap *regmap; |
|
int ret, irq; |
|
u32 reg; |
|
|
|
regmap = dev_get_regmap(dev->parent, NULL); |
|
if (!regmap) |
|
return -ENODEV; |
|
|
|
ret = of_property_read_u32(node, "reg", ®); |
|
if (ret) |
|
return ret; |
|
|
|
adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL); |
|
if (!adc_tm) |
|
return -ENOMEM; |
|
|
|
adc_tm->regmap = regmap; |
|
adc_tm->dev = dev; |
|
adc_tm->base = reg; |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) { |
|
dev_err(dev, "get_irq failed: %d\n", irq); |
|
return irq; |
|
} |
|
|
|
ret = adc_tm5_get_dt_data(adc_tm, node); |
|
if (ret) { |
|
dev_err(dev, "get dt data failed: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = adc_tm5_init(adc_tm); |
|
if (ret) { |
|
dev_err(dev, "adc-tm init failed\n"); |
|
return ret; |
|
} |
|
|
|
ret = adc_tm5_register_tzd(adc_tm); |
|
if (ret) { |
|
dev_err(dev, "tzd register failed\n"); |
|
return ret; |
|
} |
|
|
|
return devm_request_threaded_irq(dev, irq, NULL, adc_tm5_isr, |
|
IRQF_ONESHOT, "pm-adc-tm5", adc_tm); |
|
} |
|
|
|
static const struct of_device_id adc_tm5_match_table[] = { |
|
{ |
|
.compatible = "qcom,spmi-adc-tm5", |
|
.data = &adc_tm5_data_pmic, |
|
}, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, adc_tm5_match_table); |
|
|
|
static struct platform_driver adc_tm5_driver = { |
|
.driver = { |
|
.name = "qcom-spmi-adc-tm5", |
|
.of_match_table = adc_tm5_match_table, |
|
}, |
|
.probe = adc_tm5_probe, |
|
}; |
|
module_platform_driver(adc_tm5_driver); |
|
|
|
MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|