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439 lines
11 KiB
439 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* The On Chip Memory (OCMEM) allocator allows various clients to allocate |
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* memory from OCMEM based on performance, latency and power requirements. |
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* This is typically used by the GPU, camera/video, and audio components on |
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* some Snapdragon SoCs. |
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* |
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* Copyright (C) 2019 Brian Masney <[email protected]> |
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* Copyright (C) 2015 Red Hat. Author: Rob Clark <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/qcom_scm.h> |
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#include <linux/sizes.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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#include <soc/qcom/ocmem.h> |
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enum region_mode { |
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WIDE_MODE = 0x0, |
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THIN_MODE, |
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MODE_DEFAULT = WIDE_MODE, |
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}; |
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enum ocmem_macro_state { |
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PASSTHROUGH = 0, |
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PERI_ON = 1, |
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CORE_ON = 2, |
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CLK_OFF = 4, |
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}; |
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struct ocmem_region { |
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bool interleaved; |
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enum region_mode mode; |
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unsigned int num_macros; |
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enum ocmem_macro_state macro_state[4]; |
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unsigned long macro_size; |
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unsigned long region_size; |
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}; |
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struct ocmem_config { |
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uint8_t num_regions; |
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unsigned long macro_size; |
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}; |
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struct ocmem { |
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struct device *dev; |
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const struct ocmem_config *config; |
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struct resource *memory; |
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void __iomem *mmio; |
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unsigned int num_ports; |
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unsigned int num_macros; |
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bool interleaved; |
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struct ocmem_region *regions; |
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unsigned long active_allocations; |
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}; |
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#define OCMEM_MIN_ALIGN SZ_64K |
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#define OCMEM_MIN_ALLOC SZ_64K |
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#define OCMEM_REG_HW_VERSION 0x00000000 |
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#define OCMEM_REG_HW_PROFILE 0x00000004 |
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#define OCMEM_REG_REGION_MODE_CTL 0x00001000 |
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#define OCMEM_REGION_MODE_CTL_REG0_THIN 0x00000001 |
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#define OCMEM_REGION_MODE_CTL_REG1_THIN 0x00000002 |
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#define OCMEM_REGION_MODE_CTL_REG2_THIN 0x00000004 |
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#define OCMEM_REGION_MODE_CTL_REG3_THIN 0x00000008 |
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#define OCMEM_REG_GFX_MPU_START 0x00001004 |
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#define OCMEM_REG_GFX_MPU_END 0x00001008 |
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#define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_PREP(0x0000000f, (val)) |
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#define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_PREP(0x00003f00, (val)) |
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#define OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE 0x00010000 |
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#define OCMEM_HW_PROFILE_INTERLEAVING 0x00020000 |
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#define OCMEM_REG_GEN_STATUS 0x0000000c |
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#define OCMEM_REG_PSGSC_STATUS 0x00000038 |
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#define OCMEM_REG_PSGSC_CTL(i0) (0x0000003c + 0x1*(i0)) |
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#define OCMEM_PSGSC_CTL_MACRO0_MODE(val) FIELD_PREP(0x00000007, (val)) |
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#define OCMEM_PSGSC_CTL_MACRO1_MODE(val) FIELD_PREP(0x00000070, (val)) |
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#define OCMEM_PSGSC_CTL_MACRO2_MODE(val) FIELD_PREP(0x00000700, (val)) |
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#define OCMEM_PSGSC_CTL_MACRO3_MODE(val) FIELD_PREP(0x00007000, (val)) |
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#define OCMEM_CLK_CORE_IDX 0 |
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static struct clk_bulk_data ocmem_clks[] = { |
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{ |
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.id = "core", |
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}, |
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{ |
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.id = "iface", |
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}, |
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}; |
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static inline void ocmem_write(struct ocmem *ocmem, u32 reg, u32 data) |
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{ |
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writel(data, ocmem->mmio + reg); |
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} |
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static inline u32 ocmem_read(struct ocmem *ocmem, u32 reg) |
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{ |
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return readl(ocmem->mmio + reg); |
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} |
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static void update_ocmem(struct ocmem *ocmem) |
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{ |
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uint32_t region_mode_ctrl = 0x0; |
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int i; |
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if (!qcom_scm_ocmem_lock_available()) { |
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for (i = 0; i < ocmem->config->num_regions; i++) { |
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struct ocmem_region *region = &ocmem->regions[i]; |
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if (region->mode == THIN_MODE) |
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region_mode_ctrl |= BIT(i); |
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} |
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dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n", |
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region_mode_ctrl); |
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ocmem_write(ocmem, OCMEM_REG_REGION_MODE_CTL, region_mode_ctrl); |
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} |
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for (i = 0; i < ocmem->config->num_regions; i++) { |
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struct ocmem_region *region = &ocmem->regions[i]; |
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u32 data; |
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data = OCMEM_PSGSC_CTL_MACRO0_MODE(region->macro_state[0]) | |
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OCMEM_PSGSC_CTL_MACRO1_MODE(region->macro_state[1]) | |
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OCMEM_PSGSC_CTL_MACRO2_MODE(region->macro_state[2]) | |
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OCMEM_PSGSC_CTL_MACRO3_MODE(region->macro_state[3]); |
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ocmem_write(ocmem, OCMEM_REG_PSGSC_CTL(i), data); |
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} |
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} |
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static unsigned long phys_to_offset(struct ocmem *ocmem, |
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unsigned long addr) |
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{ |
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if (addr < ocmem->memory->start || addr >= ocmem->memory->end) |
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return 0; |
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return addr - ocmem->memory->start; |
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} |
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static unsigned long device_address(struct ocmem *ocmem, |
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enum ocmem_client client, |
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unsigned long addr) |
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{ |
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WARN_ON(client != OCMEM_GRAPHICS); |
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/* TODO: gpu uses phys_to_offset, but others do not.. */ |
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return phys_to_offset(ocmem, addr); |
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} |
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static void update_range(struct ocmem *ocmem, struct ocmem_buf *buf, |
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enum ocmem_macro_state mstate, enum region_mode rmode) |
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{ |
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unsigned long offset = 0; |
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int i, j; |
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for (i = 0; i < ocmem->config->num_regions; i++) { |
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struct ocmem_region *region = &ocmem->regions[i]; |
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if (buf->offset <= offset && offset < buf->offset + buf->len) |
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region->mode = rmode; |
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for (j = 0; j < region->num_macros; j++) { |
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if (buf->offset <= offset && |
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offset < buf->offset + buf->len) |
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region->macro_state[j] = mstate; |
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offset += region->macro_size; |
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} |
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} |
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update_ocmem(ocmem); |
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} |
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struct ocmem *of_get_ocmem(struct device *dev) |
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{ |
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struct platform_device *pdev; |
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struct device_node *devnode; |
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struct ocmem *ocmem; |
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devnode = of_parse_phandle(dev->of_node, "sram", 0); |
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if (!devnode || !devnode->parent) { |
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dev_err(dev, "Cannot look up sram phandle\n"); |
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return ERR_PTR(-ENODEV); |
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} |
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pdev = of_find_device_by_node(devnode->parent); |
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if (!pdev) { |
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dev_err(dev, "Cannot find device node %s\n", devnode->name); |
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return ERR_PTR(-EPROBE_DEFER); |
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} |
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ocmem = platform_get_drvdata(pdev); |
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if (!ocmem) { |
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dev_err(dev, "Cannot get ocmem\n"); |
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return ERR_PTR(-ENODEV); |
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} |
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return ocmem; |
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} |
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EXPORT_SYMBOL(of_get_ocmem); |
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struct ocmem_buf *ocmem_allocate(struct ocmem *ocmem, enum ocmem_client client, |
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unsigned long size) |
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{ |
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struct ocmem_buf *buf; |
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int ret; |
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/* TODO: add support for other clients... */ |
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if (WARN_ON(client != OCMEM_GRAPHICS)) |
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return ERR_PTR(-ENODEV); |
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if (size < OCMEM_MIN_ALLOC || !IS_ALIGNED(size, OCMEM_MIN_ALIGN)) |
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return ERR_PTR(-EINVAL); |
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if (test_and_set_bit_lock(BIT(client), &ocmem->active_allocations)) |
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return ERR_PTR(-EBUSY); |
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buf = kzalloc(sizeof(*buf), GFP_KERNEL); |
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if (!buf) { |
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ret = -ENOMEM; |
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goto err_unlock; |
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} |
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buf->offset = 0; |
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buf->addr = device_address(ocmem, client, buf->offset); |
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buf->len = size; |
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update_range(ocmem, buf, CORE_ON, WIDE_MODE); |
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if (qcom_scm_ocmem_lock_available()) { |
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ret = qcom_scm_ocmem_lock(QCOM_SCM_OCMEM_GRAPHICS_ID, |
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buf->offset, buf->len, WIDE_MODE); |
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if (ret) { |
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dev_err(ocmem->dev, "could not lock: %d\n", ret); |
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ret = -EINVAL; |
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goto err_kfree; |
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} |
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} else { |
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ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, buf->offset); |
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ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END, |
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buf->offset + buf->len); |
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} |
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dev_dbg(ocmem->dev, "using %ldK of OCMEM at 0x%08lx for client %d\n", |
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size / 1024, buf->addr, client); |
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return buf; |
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err_kfree: |
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kfree(buf); |
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err_unlock: |
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clear_bit_unlock(BIT(client), &ocmem->active_allocations); |
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return ERR_PTR(ret); |
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} |
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EXPORT_SYMBOL(ocmem_allocate); |
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void ocmem_free(struct ocmem *ocmem, enum ocmem_client client, |
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struct ocmem_buf *buf) |
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{ |
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/* TODO: add support for other clients... */ |
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if (WARN_ON(client != OCMEM_GRAPHICS)) |
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return; |
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update_range(ocmem, buf, CLK_OFF, MODE_DEFAULT); |
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if (qcom_scm_ocmem_lock_available()) { |
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int ret; |
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ret = qcom_scm_ocmem_unlock(QCOM_SCM_OCMEM_GRAPHICS_ID, |
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buf->offset, buf->len); |
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if (ret) |
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dev_err(ocmem->dev, "could not unlock: %d\n", ret); |
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} else { |
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ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, 0x0); |
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ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END, 0x0); |
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} |
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kfree(buf); |
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clear_bit_unlock(BIT(client), &ocmem->active_allocations); |
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} |
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EXPORT_SYMBOL(ocmem_free); |
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static int ocmem_dev_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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unsigned long reg, region_size; |
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int i, j, ret, num_banks; |
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struct resource *res; |
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struct ocmem *ocmem; |
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if (!qcom_scm_is_available()) |
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return -EPROBE_DEFER; |
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ocmem = devm_kzalloc(dev, sizeof(*ocmem), GFP_KERNEL); |
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if (!ocmem) |
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return -ENOMEM; |
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ocmem->dev = dev; |
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ocmem->config = device_get_match_data(dev); |
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ret = devm_clk_bulk_get(dev, ARRAY_SIZE(ocmem_clks), ocmem_clks); |
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if (ret) { |
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if (ret != -EPROBE_DEFER) |
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dev_err(dev, "Unable to get clocks\n"); |
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return ret; |
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} |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); |
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ocmem->mmio = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(ocmem->mmio)) { |
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dev_err(&pdev->dev, "Failed to ioremap ocmem_ctrl resource\n"); |
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return PTR_ERR(ocmem->mmio); |
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} |
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ocmem->memory = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
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"mem"); |
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if (!ocmem->memory) { |
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dev_err(dev, "Could not get mem region\n"); |
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return -ENXIO; |
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} |
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/* The core clock is synchronous with graphics */ |
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WARN_ON(clk_set_rate(ocmem_clks[OCMEM_CLK_CORE_IDX].clk, 1000) < 0); |
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(ocmem_clks), ocmem_clks); |
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if (ret) { |
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dev_info(ocmem->dev, "Failed to enable clocks\n"); |
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return ret; |
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} |
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if (qcom_scm_restore_sec_cfg_available()) { |
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dev_dbg(dev, "configuring scm\n"); |
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ret = qcom_scm_restore_sec_cfg(QCOM_SCM_OCMEM_DEV_ID, 0); |
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if (ret) { |
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dev_err(dev, "Could not enable secure configuration\n"); |
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goto err_clk_disable; |
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} |
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} |
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reg = ocmem_read(ocmem, OCMEM_REG_HW_PROFILE); |
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ocmem->num_ports = OCMEM_HW_PROFILE_NUM_PORTS(reg); |
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ocmem->num_macros = OCMEM_HW_PROFILE_NUM_MACROS(reg); |
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ocmem->interleaved = !!(reg & OCMEM_HW_PROFILE_INTERLEAVING); |
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num_banks = ocmem->num_ports / 2; |
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region_size = ocmem->config->macro_size * num_banks; |
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dev_info(dev, "%u ports, %u regions, %u macros, %sinterleaved\n", |
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ocmem->num_ports, ocmem->config->num_regions, |
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ocmem->num_macros, ocmem->interleaved ? "" : "not "); |
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ocmem->regions = devm_kcalloc(dev, ocmem->config->num_regions, |
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sizeof(struct ocmem_region), GFP_KERNEL); |
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if (!ocmem->regions) { |
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ret = -ENOMEM; |
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goto err_clk_disable; |
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} |
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for (i = 0; i < ocmem->config->num_regions; i++) { |
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struct ocmem_region *region = &ocmem->regions[i]; |
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if (WARN_ON(num_banks > ARRAY_SIZE(region->macro_state))) { |
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ret = -EINVAL; |
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goto err_clk_disable; |
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} |
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region->mode = MODE_DEFAULT; |
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region->num_macros = num_banks; |
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if (i == (ocmem->config->num_regions - 1) && |
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reg & OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE) { |
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region->macro_size = ocmem->config->macro_size / 2; |
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region->region_size = region_size / 2; |
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} else { |
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region->macro_size = ocmem->config->macro_size; |
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region->region_size = region_size; |
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} |
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for (j = 0; j < ARRAY_SIZE(region->macro_state); j++) |
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region->macro_state[j] = CLK_OFF; |
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} |
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platform_set_drvdata(pdev, ocmem); |
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return 0; |
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err_clk_disable: |
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clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks); |
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return ret; |
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} |
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static int ocmem_dev_remove(struct platform_device *pdev) |
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{ |
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clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks); |
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return 0; |
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} |
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static const struct ocmem_config ocmem_8974_config = { |
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.num_regions = 3, |
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.macro_size = SZ_128K, |
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}; |
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static const struct of_device_id ocmem_of_match[] = { |
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{ .compatible = "qcom,msm8974-ocmem", .data = &ocmem_8974_config }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, ocmem_of_match); |
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static struct platform_driver ocmem_driver = { |
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.probe = ocmem_dev_probe, |
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.remove = ocmem_dev_remove, |
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.driver = { |
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.name = "ocmem", |
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.of_match_table = ocmem_of_match, |
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}, |
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}; |
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module_platform_driver(ocmem_driver); |
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MODULE_DESCRIPTION("On Chip Memory (OCMEM) allocator for some Snapdragon SoCs"); |
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MODULE_LICENSE("GPL v2");
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