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272 lines
7.3 KiB
272 lines
7.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
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*/ |
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#ifndef UFS_QCOM_H_ |
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#define UFS_QCOM_H_ |
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#include <linux/reset-controller.h> |
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#include <linux/reset.h> |
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#define MAX_UFS_QCOM_HOSTS 1 |
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#define MAX_U32 (~(u32)0) |
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#define MPHY_TX_FSM_STATE 0x41 |
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#define TX_FSM_HIBERN8 0x1 |
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#define HBRN8_POLL_TOUT_MS 100 |
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#define DEFAULT_CLK_RATE_HZ 1000000 |
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#define BUS_VECTOR_NAME_LEN 32 |
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#define UFS_HW_VER_MAJOR_SHFT (28) |
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#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) |
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#define UFS_HW_VER_MINOR_SHFT (16) |
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#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) |
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#define UFS_HW_VER_STEP_SHFT (0) |
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#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) |
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/* vendor specific pre-defined parameters */ |
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#define SLOW 1 |
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#define FAST 2 |
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#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B |
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/* QCOM UFS host controller vendor specific registers */ |
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enum { |
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REG_UFS_SYS1CLK_1US = 0xC0, |
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REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4, |
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REG_UFS_LOCAL_PORT_ID_REG = 0xC8, |
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REG_UFS_PA_ERR_CODE = 0xCC, |
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REG_UFS_RETRY_TIMER_REG = 0xD0, |
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REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8, |
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REG_UFS_CFG1 = 0xDC, |
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REG_UFS_CFG2 = 0xE0, |
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REG_UFS_HW_VERSION = 0xE4, |
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UFS_TEST_BUS = 0xE8, |
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UFS_TEST_BUS_CTRL_0 = 0xEC, |
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UFS_TEST_BUS_CTRL_1 = 0xF0, |
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UFS_TEST_BUS_CTRL_2 = 0xF4, |
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UFS_UNIPRO_CFG = 0xF8, |
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/* |
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* QCOM UFS host controller vendor specific registers |
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* added in HW Version 3.0.0 |
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*/ |
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UFS_AH8_CFG = 0xFC, |
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}; |
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/* QCOM UFS host controller vendor specific debug registers */ |
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enum { |
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UFS_DBG_RD_REG_UAWM = 0x100, |
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UFS_DBG_RD_REG_UARM = 0x200, |
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UFS_DBG_RD_REG_TXUC = 0x300, |
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UFS_DBG_RD_REG_RXUC = 0x400, |
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UFS_DBG_RD_REG_DFC = 0x500, |
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UFS_DBG_RD_REG_TRLUT = 0x600, |
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UFS_DBG_RD_REG_TMRLUT = 0x700, |
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UFS_UFS_DBG_RD_REG_OCSC = 0x800, |
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UFS_UFS_DBG_RD_DESC_RAM = 0x1500, |
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UFS_UFS_DBG_RD_PRDT_RAM = 0x1700, |
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UFS_UFS_DBG_RD_RESP_RAM = 0x1800, |
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UFS_UFS_DBG_RD_EDTL_RAM = 0x1900, |
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}; |
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#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) |
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#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) |
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/* bit definitions for REG_UFS_CFG1 register */ |
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#define QUNIPRO_SEL 0x1 |
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#define UTP_DBG_RAMS_EN 0x20000 |
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#define TEST_BUS_EN BIT(18) |
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#define TEST_BUS_SEL GENMASK(22, 19) |
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#define UFS_REG_TEST_BUS_EN BIT(30) |
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/* bit definitions for REG_UFS_CFG2 register */ |
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#define UAWM_HW_CGC_EN (1 << 0) |
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#define UARM_HW_CGC_EN (1 << 1) |
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#define TXUC_HW_CGC_EN (1 << 2) |
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#define RXUC_HW_CGC_EN (1 << 3) |
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#define DFC_HW_CGC_EN (1 << 4) |
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#define TRLUT_HW_CGC_EN (1 << 5) |
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#define TMRLUT_HW_CGC_EN (1 << 6) |
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#define OCSC_HW_CGC_EN (1 << 7) |
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/* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ |
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#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide */ |
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#define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ |
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TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ |
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DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\ |
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TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) |
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/* bit offset */ |
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enum { |
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OFFSET_UFS_PHY_SOFT_RESET = 1, |
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OFFSET_CLK_NS_REG = 10, |
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}; |
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/* bit masks */ |
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enum { |
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MASK_UFS_PHY_SOFT_RESET = 0x2, |
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MASK_TX_SYMBOL_CLK_1US_REG = 0x3FF, |
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MASK_CLK_NS_REG = 0xFFFC00, |
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}; |
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/* QCOM UFS debug print bit mask */ |
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#define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0) |
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#define UFS_QCOM_DBG_PRINT_ICE_REGS_EN BIT(1) |
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#define UFS_QCOM_DBG_PRINT_TEST_BUS_EN BIT(2) |
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#define UFS_QCOM_DBG_PRINT_ALL \ |
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(UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \ |
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UFS_QCOM_DBG_PRINT_TEST_BUS_EN) |
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/* QUniPro Vendor specific attributes */ |
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#define PA_VS_CONFIG_REG1 0x9000 |
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#define DME_VS_CORE_CLK_CTRL 0xD002 |
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/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ |
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#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) |
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#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF |
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static inline void |
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ufs_qcom_get_controller_revision(struct ufs_hba *hba, |
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u8 *major, u16 *minor, u16 *step) |
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{ |
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u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); |
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*major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT; |
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*minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT; |
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*step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT; |
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}; |
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static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) |
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{ |
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ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, |
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1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); |
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/* |
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* Make sure assertion of ufs phy reset is written to |
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* register before returning |
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*/ |
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mb(); |
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} |
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static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) |
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{ |
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ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, |
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0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); |
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/* |
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* Make sure de-assertion of ufs phy reset is written to |
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* register before returning |
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*/ |
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mb(); |
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} |
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/* Host controller hardware version: major.minor.step */ |
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struct ufs_hw_version { |
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u16 step; |
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u16 minor; |
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u8 major; |
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}; |
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struct ufs_qcom_testbus { |
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u8 select_major; |
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u8 select_minor; |
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}; |
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struct gpio_desc; |
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struct ufs_qcom_host { |
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/* |
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* Set this capability if host controller supports the QUniPro mode |
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* and if driver wants the Host controller to operate in QUniPro mode. |
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* Note: By default this capability will be kept enabled if host |
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* controller supports the QUniPro mode. |
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*/ |
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#define UFS_QCOM_CAP_QUNIPRO 0x1 |
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/* |
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* Set this capability if host controller can retain the secure |
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* configuration even after UFS controller core power collapse. |
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*/ |
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#define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE 0x2 |
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u32 caps; |
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struct phy *generic_phy; |
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struct ufs_hba *hba; |
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struct ufs_pa_layer_attr dev_req_params; |
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struct clk *rx_l0_sync_clk; |
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struct clk *tx_l0_sync_clk; |
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struct clk *rx_l1_sync_clk; |
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struct clk *tx_l1_sync_clk; |
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bool is_lane_clks_enabled; |
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void __iomem *dev_ref_clk_ctrl_mmio; |
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bool is_dev_ref_clk_enabled; |
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struct ufs_hw_version hw_ver; |
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#ifdef CONFIG_SCSI_UFS_CRYPTO |
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void __iomem *ice_mmio; |
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#endif |
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u32 dev_ref_clk_en_mask; |
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/* Bitmask for enabling debug prints */ |
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u32 dbg_print_en; |
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struct ufs_qcom_testbus testbus; |
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/* Reset control of HCI */ |
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struct reset_control *core_reset; |
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struct reset_controller_dev rcdev; |
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struct gpio_desc *device_reset; |
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}; |
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static inline u32 |
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ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg) |
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{ |
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if (host->hw_ver.major <= 0x02) |
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return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg); |
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return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg); |
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}; |
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#define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba) |
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#define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba) |
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#define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba) |
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int ufs_qcom_testbus_config(struct ufs_qcom_host *host); |
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static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host) |
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{ |
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if (host->caps & UFS_QCOM_CAP_QUNIPRO) |
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return true; |
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else |
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return false; |
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} |
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/* ufs-qcom-ice.c */ |
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#ifdef CONFIG_SCSI_UFS_CRYPTO |
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int ufs_qcom_ice_init(struct ufs_qcom_host *host); |
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int ufs_qcom_ice_enable(struct ufs_qcom_host *host); |
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int ufs_qcom_ice_resume(struct ufs_qcom_host *host); |
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int ufs_qcom_ice_program_key(struct ufs_hba *hba, |
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const union ufs_crypto_cfg_entry *cfg, int slot); |
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#else |
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static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host) |
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{ |
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return 0; |
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} |
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static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host) |
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{ |
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return 0; |
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} |
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static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) |
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{ |
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return 0; |
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} |
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#define ufs_qcom_ice_program_key NULL |
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#endif /* !CONFIG_SCSI_UFS_CRYPTO */ |
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#endif /* UFS_QCOM_H_ */
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