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281 lines
6.6 KiB
281 lines
6.6 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* APM X-Gene SoC Real Time Clock Driver |
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* |
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* Copyright (c) 2014, Applied Micro Circuits Corporation |
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* Author: Rameshwar Prasad Sahu <[email protected]> |
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* Loc Ho <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/rtc.h> |
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#include <linux/slab.h> |
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/* RTC CSR Registers */ |
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#define RTC_CCVR 0x00 |
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#define RTC_CMR 0x04 |
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#define RTC_CLR 0x08 |
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#define RTC_CCR 0x0C |
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#define RTC_CCR_IE BIT(0) |
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#define RTC_CCR_MASK BIT(1) |
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#define RTC_CCR_EN BIT(2) |
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#define RTC_CCR_WEN BIT(3) |
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#define RTC_STAT 0x10 |
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#define RTC_STAT_BIT BIT(0) |
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#define RTC_RSTAT 0x14 |
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#define RTC_EOI 0x18 |
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#define RTC_VER 0x1C |
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struct xgene_rtc_dev { |
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struct rtc_device *rtc; |
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void __iomem *csr_base; |
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struct clk *clk; |
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unsigned int irq_wake; |
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unsigned int irq_enabled; |
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}; |
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static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm) |
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{ |
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struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); |
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rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm); |
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return 0; |
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} |
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static int xgene_rtc_set_time(struct device *dev, struct rtc_time *tm) |
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{ |
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struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); |
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/* |
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* NOTE: After the following write, the RTC_CCVR is only reflected |
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* after the update cycle of 1 seconds. |
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*/ |
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writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR); |
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readl(pdata->csr_base + RTC_CLR); /* Force a barrier */ |
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return 0; |
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} |
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static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
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{ |
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struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); |
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/* If possible, CMR should be read here */ |
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rtc_time64_to_tm(0, &alrm->time); |
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alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE; |
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return 0; |
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} |
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static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled) |
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{ |
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struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); |
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u32 ccr; |
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ccr = readl(pdata->csr_base + RTC_CCR); |
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if (enabled) { |
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ccr &= ~RTC_CCR_MASK; |
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ccr |= RTC_CCR_IE; |
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} else { |
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ccr &= ~RTC_CCR_IE; |
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ccr |= RTC_CCR_MASK; |
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} |
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writel(ccr, pdata->csr_base + RTC_CCR); |
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return 0; |
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} |
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static int xgene_rtc_alarm_irq_enabled(struct device *dev) |
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{ |
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struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); |
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return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0; |
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} |
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static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
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{ |
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struct xgene_rtc_dev *pdata = dev_get_drvdata(dev); |
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writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR); |
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xgene_rtc_alarm_irq_enable(dev, alrm->enabled); |
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return 0; |
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} |
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static const struct rtc_class_ops xgene_rtc_ops = { |
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.read_time = xgene_rtc_read_time, |
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.set_time = xgene_rtc_set_time, |
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.read_alarm = xgene_rtc_read_alarm, |
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.set_alarm = xgene_rtc_set_alarm, |
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.alarm_irq_enable = xgene_rtc_alarm_irq_enable, |
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}; |
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static irqreturn_t xgene_rtc_interrupt(int irq, void *id) |
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{ |
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struct xgene_rtc_dev *pdata = id; |
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/* Check if interrupt asserted */ |
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if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT)) |
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return IRQ_NONE; |
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/* Clear interrupt */ |
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readl(pdata->csr_base + RTC_EOI); |
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rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF); |
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return IRQ_HANDLED; |
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} |
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static int xgene_rtc_probe(struct platform_device *pdev) |
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{ |
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struct xgene_rtc_dev *pdata; |
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int ret; |
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int irq; |
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
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if (!pdata) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, pdata); |
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pdata->csr_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(pdata->csr_base)) |
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return PTR_ERR(pdata->csr_base); |
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pdata->rtc = devm_rtc_allocate_device(&pdev->dev); |
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if (IS_ERR(pdata->rtc)) |
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return PTR_ERR(pdata->rtc); |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0, |
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dev_name(&pdev->dev), pdata); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not request IRQ\n"); |
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return ret; |
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} |
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pdata->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(pdata->clk)) { |
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dev_err(&pdev->dev, "Couldn't get the clock for RTC\n"); |
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return -ENODEV; |
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} |
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ret = clk_prepare_enable(pdata->clk); |
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if (ret) |
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return ret; |
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/* Turn on the clock and the crystal */ |
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writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR); |
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ret = device_init_wakeup(&pdev->dev, 1); |
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if (ret) { |
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clk_disable_unprepare(pdata->clk); |
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return ret; |
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} |
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/* HW does not support update faster than 1 seconds */ |
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pdata->rtc->uie_unsupported = 1; |
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pdata->rtc->ops = &xgene_rtc_ops; |
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pdata->rtc->range_max = U32_MAX; |
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ret = devm_rtc_register_device(pdata->rtc); |
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if (ret) { |
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clk_disable_unprepare(pdata->clk); |
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return ret; |
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} |
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return 0; |
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} |
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static int xgene_rtc_remove(struct platform_device *pdev) |
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{ |
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struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev); |
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xgene_rtc_alarm_irq_enable(&pdev->dev, 0); |
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device_init_wakeup(&pdev->dev, 0); |
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clk_disable_unprepare(pdata->clk); |
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return 0; |
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} |
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static int __maybe_unused xgene_rtc_suspend(struct device *dev) |
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{ |
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struct platform_device *pdev = to_platform_device(dev); |
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struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev); |
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int irq; |
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irq = platform_get_irq(pdev, 0); |
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/* |
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* If this RTC alarm will be used for waking the system up, |
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* don't disable it of course. Else we just disable the alarm |
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* and await suspension. |
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*/ |
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if (device_may_wakeup(&pdev->dev)) { |
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if (!enable_irq_wake(irq)) |
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pdata->irq_wake = 1; |
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} else { |
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pdata->irq_enabled = xgene_rtc_alarm_irq_enabled(dev); |
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xgene_rtc_alarm_irq_enable(dev, 0); |
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clk_disable_unprepare(pdata->clk); |
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} |
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return 0; |
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} |
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static int __maybe_unused xgene_rtc_resume(struct device *dev) |
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{ |
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struct platform_device *pdev = to_platform_device(dev); |
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struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev); |
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int irq; |
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int rc; |
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irq = platform_get_irq(pdev, 0); |
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if (device_may_wakeup(&pdev->dev)) { |
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if (pdata->irq_wake) { |
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disable_irq_wake(irq); |
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pdata->irq_wake = 0; |
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} |
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} else { |
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rc = clk_prepare_enable(pdata->clk); |
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if (rc) { |
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dev_err(dev, "Unable to enable clock error %d\n", rc); |
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return rc; |
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} |
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xgene_rtc_alarm_irq_enable(dev, pdata->irq_enabled); |
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} |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume); |
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#ifdef CONFIG_OF |
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static const struct of_device_id xgene_rtc_of_match[] = { |
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{.compatible = "apm,xgene-rtc" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, xgene_rtc_of_match); |
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#endif |
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static struct platform_driver xgene_rtc_driver = { |
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.probe = xgene_rtc_probe, |
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.remove = xgene_rtc_remove, |
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.driver = { |
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.name = "xgene-rtc", |
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.pm = &xgene_rtc_pm_ops, |
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.of_match_table = of_match_ptr(xgene_rtc_of_match), |
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}, |
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}; |
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module_platform_driver(xgene_rtc_driver); |
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MODULE_DESCRIPTION("APM X-Gene SoC RTC driver"); |
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MODULE_AUTHOR("Rameshwar Sahu <[email protected]>"); |
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MODULE_LICENSE("GPL");
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