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654 lines
17 KiB
654 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Real Time Clock interface for Linux on Atmel AT91RM9200 |
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* |
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* Copyright (C) 2002 Rick Bronson |
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* |
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* Converted to RTC class model by Andrew Victor |
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* |
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* Ported to Linux 2.6 by Steven Scholz |
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* Based on s3c2410-rtc.c Simtec Electronics |
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* |
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* Based on sa1100-rtc.c by Nils Faerber |
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* Based on rtc.c by Paul Gortmaker |
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*/ |
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#include <linux/bcd.h> |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/interrupt.h> |
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#include <linux/ioctl.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/rtc.h> |
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#include <linux/spinlock.h> |
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#include <linux/suspend.h> |
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#include <linux/time.h> |
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#include <linux/uaccess.h> |
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#define AT91_RTC_CR 0x00 /* Control Register */ |
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#define AT91_RTC_UPDTIM BIT(0) /* Update Request Time Register */ |
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#define AT91_RTC_UPDCAL BIT(1) /* Update Request Calendar Register */ |
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#define AT91_RTC_MR 0x04 /* Mode Register */ |
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#define AT91_RTC_HRMOD BIT(0) /* 12/24 hour mode */ |
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#define AT91_RTC_NEGPPM BIT(4) /* Negative PPM correction */ |
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#define AT91_RTC_CORRECTION GENMASK(14, 8) /* Slow clock correction */ |
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#define AT91_RTC_HIGHPPM BIT(15) /* High PPM correction */ |
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#define AT91_RTC_TIMR 0x08 /* Time Register */ |
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#define AT91_RTC_SEC GENMASK(6, 0) /* Current Second */ |
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#define AT91_RTC_MIN GENMASK(14, 8) /* Current Minute */ |
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#define AT91_RTC_HOUR GENMASK(21, 16) /* Current Hour */ |
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#define AT91_RTC_AMPM BIT(22) /* Ante Meridiem Post Meridiem Indicator */ |
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#define AT91_RTC_CALR 0x0c /* Calendar Register */ |
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#define AT91_RTC_CENT GENMASK(6, 0) /* Current Century */ |
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#define AT91_RTC_YEAR GENMASK(15, 8) /* Current Year */ |
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#define AT91_RTC_MONTH GENMASK(20, 16) /* Current Month */ |
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#define AT91_RTC_DAY GENMASK(23, 21) /* Current Day */ |
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#define AT91_RTC_DATE GENMASK(29, 24) /* Current Date */ |
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#define AT91_RTC_TIMALR 0x10 /* Time Alarm Register */ |
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#define AT91_RTC_SECEN BIT(7) /* Second Alarm Enable */ |
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#define AT91_RTC_MINEN BIT(15) /* Minute Alarm Enable */ |
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#define AT91_RTC_HOUREN BIT(23) /* Hour Alarm Enable */ |
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#define AT91_RTC_CALALR 0x14 /* Calendar Alarm Register */ |
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#define AT91_RTC_MTHEN BIT(23) /* Month Alarm Enable */ |
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#define AT91_RTC_DATEEN BIT(31) /* Date Alarm Enable */ |
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#define AT91_RTC_SR 0x18 /* Status Register */ |
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#define AT91_RTC_ACKUPD BIT(0) /* Acknowledge for Update */ |
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#define AT91_RTC_ALARM BIT(1) /* Alarm Flag */ |
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#define AT91_RTC_SECEV BIT(2) /* Second Event */ |
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#define AT91_RTC_TIMEV BIT(3) /* Time Event */ |
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#define AT91_RTC_CALEV BIT(4) /* Calendar Event */ |
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#define AT91_RTC_SCCR 0x1c /* Status Clear Command Register */ |
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#define AT91_RTC_IER 0x20 /* Interrupt Enable Register */ |
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#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */ |
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#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */ |
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#define AT91_RTC_VER 0x2c /* Valid Entry Register */ |
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#define AT91_RTC_NVTIM BIT(0) /* Non valid Time */ |
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#define AT91_RTC_NVCAL BIT(1) /* Non valid Calendar */ |
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#define AT91_RTC_NVTIMALR BIT(2) /* Non valid Time Alarm */ |
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#define AT91_RTC_NVCALALR BIT(3) /* Non valid Calendar Alarm */ |
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#define AT91_RTC_CORR_DIVIDEND 3906000 |
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#define AT91_RTC_CORR_LOW_RATIO 20 |
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#define at91_rtc_read(field) \ |
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readl_relaxed(at91_rtc_regs + field) |
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#define at91_rtc_write(field, val) \ |
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writel_relaxed((val), at91_rtc_regs + field) |
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struct at91_rtc_config { |
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bool use_shadow_imr; |
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bool has_correction; |
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}; |
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static const struct at91_rtc_config *at91_rtc_config; |
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static DECLARE_COMPLETION(at91_rtc_updated); |
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static DECLARE_COMPLETION(at91_rtc_upd_rdy); |
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static void __iomem *at91_rtc_regs; |
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static int irq; |
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static DEFINE_SPINLOCK(at91_rtc_lock); |
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static u32 at91_rtc_shadow_imr; |
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static bool suspended; |
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static DEFINE_SPINLOCK(suspended_lock); |
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static unsigned long cached_events; |
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static u32 at91_rtc_imr; |
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static struct clk *sclk; |
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static void at91_rtc_write_ier(u32 mask) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&at91_rtc_lock, flags); |
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at91_rtc_shadow_imr |= mask; |
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at91_rtc_write(AT91_RTC_IER, mask); |
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spin_unlock_irqrestore(&at91_rtc_lock, flags); |
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} |
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static void at91_rtc_write_idr(u32 mask) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&at91_rtc_lock, flags); |
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at91_rtc_write(AT91_RTC_IDR, mask); |
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/* |
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* Register read back (of any RTC-register) needed to make sure |
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* IDR-register write has reached the peripheral before updating |
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* shadow mask. |
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* |
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* Note that there is still a possibility that the mask is updated |
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* before interrupts have actually been disabled in hardware. The only |
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* way to be certain would be to poll the IMR-register, which is is |
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* the very register we are trying to emulate. The register read back |
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* is a reasonable heuristic. |
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*/ |
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at91_rtc_read(AT91_RTC_SR); |
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at91_rtc_shadow_imr &= ~mask; |
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spin_unlock_irqrestore(&at91_rtc_lock, flags); |
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} |
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static u32 at91_rtc_read_imr(void) |
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{ |
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unsigned long flags; |
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u32 mask; |
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if (at91_rtc_config->use_shadow_imr) { |
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spin_lock_irqsave(&at91_rtc_lock, flags); |
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mask = at91_rtc_shadow_imr; |
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spin_unlock_irqrestore(&at91_rtc_lock, flags); |
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} else { |
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mask = at91_rtc_read(AT91_RTC_IMR); |
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} |
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return mask; |
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} |
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/* |
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* Decode time/date into rtc_time structure |
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*/ |
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static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg, |
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struct rtc_time *tm) |
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{ |
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unsigned int time, date; |
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/* must read twice in case it changes */ |
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do { |
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time = at91_rtc_read(timereg); |
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date = at91_rtc_read(calreg); |
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} while ((time != at91_rtc_read(timereg)) || |
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(date != at91_rtc_read(calreg))); |
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tm->tm_sec = bcd2bin(FIELD_GET(AT91_RTC_SEC, time)); |
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tm->tm_min = bcd2bin(FIELD_GET(AT91_RTC_MIN, time)); |
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tm->tm_hour = bcd2bin(FIELD_GET(AT91_RTC_HOUR, time)); |
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/* |
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* The Calendar Alarm register does not have a field for |
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* the year - so these will return an invalid value. |
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*/ |
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tm->tm_year = bcd2bin(date & AT91_RTC_CENT) * 100; /* century */ |
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tm->tm_year += bcd2bin(FIELD_GET(AT91_RTC_YEAR, date)); /* year */ |
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tm->tm_wday = bcd2bin(FIELD_GET(AT91_RTC_DAY, date)) - 1; /* day of the week [0-6], Sunday=0 */ |
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tm->tm_mon = bcd2bin(FIELD_GET(AT91_RTC_MONTH, date)) - 1; |
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tm->tm_mday = bcd2bin(FIELD_GET(AT91_RTC_DATE, date)); |
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} |
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/* |
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* Read current time and date in RTC |
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*/ |
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static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm) |
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{ |
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at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm); |
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tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); |
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tm->tm_year = tm->tm_year - 1900; |
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dev_dbg(dev, "%s(): %ptR\n", __func__, tm); |
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return 0; |
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} |
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/* |
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* Set current time and date in RTC |
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*/ |
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static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) |
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{ |
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unsigned long cr; |
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dev_dbg(dev, "%s(): %ptR\n", __func__, tm); |
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wait_for_completion(&at91_rtc_upd_rdy); |
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/* Stop Time/Calendar from counting */ |
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cr = at91_rtc_read(AT91_RTC_CR); |
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at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM); |
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at91_rtc_write_ier(AT91_RTC_ACKUPD); |
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wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */ |
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at91_rtc_write_idr(AT91_RTC_ACKUPD); |
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at91_rtc_write(AT91_RTC_TIMR, |
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FIELD_PREP(AT91_RTC_SEC, bin2bcd(tm->tm_sec)) |
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| FIELD_PREP(AT91_RTC_MIN, bin2bcd(tm->tm_min)) |
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| FIELD_PREP(AT91_RTC_HOUR, bin2bcd(tm->tm_hour))); |
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at91_rtc_write(AT91_RTC_CALR, |
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FIELD_PREP(AT91_RTC_CENT, |
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bin2bcd((tm->tm_year + 1900) / 100)) |
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| FIELD_PREP(AT91_RTC_YEAR, bin2bcd(tm->tm_year % 100)) |
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| FIELD_PREP(AT91_RTC_MONTH, bin2bcd(tm->tm_mon + 1)) |
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| FIELD_PREP(AT91_RTC_DAY, bin2bcd(tm->tm_wday + 1)) |
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| FIELD_PREP(AT91_RTC_DATE, bin2bcd(tm->tm_mday))); |
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/* Restart Time/Calendar */ |
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cr = at91_rtc_read(AT91_RTC_CR); |
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at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV); |
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at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM)); |
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at91_rtc_write_ier(AT91_RTC_SECEV); |
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return 0; |
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} |
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/* |
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* Read alarm time and date in RTC |
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*/ |
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static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) |
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{ |
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struct rtc_time *tm = &alrm->time; |
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at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm); |
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tm->tm_year = -1; |
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alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM) |
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? 1 : 0; |
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dev_dbg(dev, "%s(): %ptR %sabled\n", __func__, tm, |
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alrm->enabled ? "en" : "dis"); |
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return 0; |
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} |
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/* |
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* Set alarm time and date in RTC |
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*/ |
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static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) |
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{ |
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struct rtc_time tm = alrm->time; |
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at91_rtc_write_idr(AT91_RTC_ALARM); |
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at91_rtc_write(AT91_RTC_TIMALR, |
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FIELD_PREP(AT91_RTC_SEC, bin2bcd(alrm->time.tm_sec)) |
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| FIELD_PREP(AT91_RTC_MIN, bin2bcd(alrm->time.tm_min)) |
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| FIELD_PREP(AT91_RTC_HOUR, bin2bcd(alrm->time.tm_hour)) |
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| AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN); |
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at91_rtc_write(AT91_RTC_CALALR, |
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FIELD_PREP(AT91_RTC_MONTH, bin2bcd(alrm->time.tm_mon + 1)) |
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| FIELD_PREP(AT91_RTC_DATE, bin2bcd(alrm->time.tm_mday)) |
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| AT91_RTC_DATEEN | AT91_RTC_MTHEN); |
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if (alrm->enabled) { |
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at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
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at91_rtc_write_ier(AT91_RTC_ALARM); |
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} |
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dev_dbg(dev, "%s(): %ptR\n", __func__, &tm); |
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return 0; |
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} |
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static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
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{ |
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dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled); |
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if (enabled) { |
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at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
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at91_rtc_write_ier(AT91_RTC_ALARM); |
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} else |
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at91_rtc_write_idr(AT91_RTC_ALARM); |
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return 0; |
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} |
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static int at91_rtc_readoffset(struct device *dev, long *offset) |
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{ |
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u32 mr = at91_rtc_read(AT91_RTC_MR); |
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long val = FIELD_GET(AT91_RTC_CORRECTION, mr); |
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if (!val) { |
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*offset = 0; |
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return 0; |
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} |
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val++; |
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if (!(mr & AT91_RTC_NEGPPM)) |
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val = -val; |
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if (!(mr & AT91_RTC_HIGHPPM)) |
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val *= AT91_RTC_CORR_LOW_RATIO; |
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*offset = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, val); |
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return 0; |
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} |
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static int at91_rtc_setoffset(struct device *dev, long offset) |
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{ |
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long corr; |
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u32 mr; |
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if (offset > AT91_RTC_CORR_DIVIDEND / 2) |
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return -ERANGE; |
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if (offset < -AT91_RTC_CORR_DIVIDEND / 2) |
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return -ERANGE; |
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mr = at91_rtc_read(AT91_RTC_MR); |
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mr &= ~(AT91_RTC_NEGPPM | AT91_RTC_CORRECTION | AT91_RTC_HIGHPPM); |
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if (offset > 0) |
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mr |= AT91_RTC_NEGPPM; |
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else |
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offset = -offset; |
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/* offset less than 764 ppb, disable correction*/ |
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if (offset < 764) { |
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at91_rtc_write(AT91_RTC_MR, mr & ~AT91_RTC_NEGPPM); |
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return 0; |
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} |
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/* |
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* 29208 ppb is the perfect cutoff between low range and high range |
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* low range values are never better than high range value after that. |
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*/ |
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if (offset < 29208) { |
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corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset * AT91_RTC_CORR_LOW_RATIO); |
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} else { |
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corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset); |
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mr |= AT91_RTC_HIGHPPM; |
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} |
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if (corr > 128) |
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corr = 128; |
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mr |= FIELD_PREP(AT91_RTC_CORRECTION, corr - 1); |
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at91_rtc_write(AT91_RTC_MR, mr); |
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return 0; |
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} |
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/* |
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* IRQ handler for the RTC |
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*/ |
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static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id) |
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{ |
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struct platform_device *pdev = dev_id; |
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struct rtc_device *rtc = platform_get_drvdata(pdev); |
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unsigned int rtsr; |
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unsigned long events = 0; |
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int ret = IRQ_NONE; |
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spin_lock(&suspended_lock); |
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rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr(); |
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if (rtsr) { /* this interrupt is shared! Is it ours? */ |
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if (rtsr & AT91_RTC_ALARM) |
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events |= (RTC_AF | RTC_IRQF); |
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if (rtsr & AT91_RTC_SECEV) { |
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complete(&at91_rtc_upd_rdy); |
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at91_rtc_write_idr(AT91_RTC_SECEV); |
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} |
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if (rtsr & AT91_RTC_ACKUPD) |
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complete(&at91_rtc_updated); |
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at91_rtc_write(AT91_RTC_SCCR, rtsr); /* clear status reg */ |
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if (!suspended) { |
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rtc_update_irq(rtc, 1, events); |
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dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n", |
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__func__, events >> 8, events & 0x000000FF); |
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} else { |
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cached_events |= events; |
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at91_rtc_write_idr(at91_rtc_imr); |
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pm_system_wakeup(); |
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} |
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ret = IRQ_HANDLED; |
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} |
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spin_unlock(&suspended_lock); |
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return ret; |
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} |
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static const struct at91_rtc_config at91rm9200_config = { |
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}; |
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static const struct at91_rtc_config at91sam9x5_config = { |
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.use_shadow_imr = true, |
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}; |
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static const struct at91_rtc_config sama5d4_config = { |
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.has_correction = true, |
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}; |
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static const struct of_device_id at91_rtc_dt_ids[] = { |
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{ |
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.compatible = "atmel,at91rm9200-rtc", |
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.data = &at91rm9200_config, |
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}, { |
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.compatible = "atmel,at91sam9x5-rtc", |
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.data = &at91sam9x5_config, |
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}, { |
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.compatible = "atmel,sama5d4-rtc", |
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.data = &sama5d4_config, |
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}, { |
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.compatible = "atmel,sama5d2-rtc", |
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.data = &sama5d4_config, |
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}, { |
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.compatible = "microchip,sam9x60-rtc", |
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.data = &sama5d4_config, |
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}, { |
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/* sentinel */ |
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} |
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}; |
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MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids); |
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static const struct rtc_class_ops at91_rtc_ops = { |
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.read_time = at91_rtc_readtime, |
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.set_time = at91_rtc_settime, |
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.read_alarm = at91_rtc_readalarm, |
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.set_alarm = at91_rtc_setalarm, |
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.alarm_irq_enable = at91_rtc_alarm_irq_enable, |
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}; |
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static const struct rtc_class_ops sama5d4_rtc_ops = { |
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.read_time = at91_rtc_readtime, |
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.set_time = at91_rtc_settime, |
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.read_alarm = at91_rtc_readalarm, |
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.set_alarm = at91_rtc_setalarm, |
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.alarm_irq_enable = at91_rtc_alarm_irq_enable, |
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.set_offset = at91_rtc_setoffset, |
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.read_offset = at91_rtc_readoffset, |
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}; |
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/* |
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* Initialize and install RTC driver |
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*/ |
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static int __init at91_rtc_probe(struct platform_device *pdev) |
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{ |
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struct rtc_device *rtc; |
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struct resource *regs; |
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int ret = 0; |
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at91_rtc_config = of_device_get_match_data(&pdev->dev); |
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if (!at91_rtc_config) |
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return -ENODEV; |
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!regs) { |
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dev_err(&pdev->dev, "no mmio resource defined\n"); |
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return -ENXIO; |
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} |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return -ENXIO; |
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at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start, |
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resource_size(regs)); |
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if (!at91_rtc_regs) { |
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dev_err(&pdev->dev, "failed to map registers, aborting.\n"); |
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return -ENOMEM; |
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} |
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rtc = devm_rtc_allocate_device(&pdev->dev); |
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if (IS_ERR(rtc)) |
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return PTR_ERR(rtc); |
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platform_set_drvdata(pdev, rtc); |
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sclk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(sclk)) |
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return PTR_ERR(sclk); |
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ret = clk_prepare_enable(sclk); |
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if (ret) { |
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dev_err(&pdev->dev, "Could not enable slow clock\n"); |
|
return ret; |
|
} |
|
|
|
at91_rtc_write(AT91_RTC_CR, 0); |
|
at91_rtc_write(AT91_RTC_MR, at91_rtc_read(AT91_RTC_MR) & ~AT91_RTC_HRMOD); |
|
|
|
/* Disable all interrupts */ |
|
at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM | |
|
AT91_RTC_SECEV | AT91_RTC_TIMEV | |
|
AT91_RTC_CALEV); |
|
|
|
ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt, |
|
IRQF_SHARED | IRQF_COND_SUSPEND, |
|
"at91_rtc", pdev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "IRQ %d already in use.\n", irq); |
|
goto err_clk; |
|
} |
|
|
|
/* cpu init code should really have flagged this device as |
|
* being wake-capable; if it didn't, do that here. |
|
*/ |
|
if (!device_can_wakeup(&pdev->dev)) |
|
device_init_wakeup(&pdev->dev, 1); |
|
|
|
if (at91_rtc_config->has_correction) |
|
rtc->ops = &sama5d4_rtc_ops; |
|
else |
|
rtc->ops = &at91_rtc_ops; |
|
|
|
rtc->range_min = RTC_TIMESTAMP_BEGIN_1900; |
|
rtc->range_max = RTC_TIMESTAMP_END_2099; |
|
ret = devm_rtc_register_device(rtc); |
|
if (ret) |
|
goto err_clk; |
|
|
|
/* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy |
|
* completion. |
|
*/ |
|
at91_rtc_write_ier(AT91_RTC_SECEV); |
|
|
|
dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n"); |
|
return 0; |
|
|
|
err_clk: |
|
clk_disable_unprepare(sclk); |
|
|
|
return ret; |
|
} |
|
|
|
/* |
|
* Disable and remove the RTC driver |
|
*/ |
|
static int __exit at91_rtc_remove(struct platform_device *pdev) |
|
{ |
|
/* Disable all interrupts */ |
|
at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM | |
|
AT91_RTC_SECEV | AT91_RTC_TIMEV | |
|
AT91_RTC_CALEV); |
|
|
|
clk_disable_unprepare(sclk); |
|
|
|
return 0; |
|
} |
|
|
|
static void at91_rtc_shutdown(struct platform_device *pdev) |
|
{ |
|
/* Disable all interrupts */ |
|
at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM | |
|
AT91_RTC_SECEV | AT91_RTC_TIMEV | |
|
AT91_RTC_CALEV); |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
|
|
/* AT91RM9200 RTC Power management control */ |
|
|
|
static int at91_rtc_suspend(struct device *dev) |
|
{ |
|
/* this IRQ is shared with DBGU and other hardware which isn't |
|
* necessarily doing PM like we are... |
|
*/ |
|
at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM); |
|
|
|
at91_rtc_imr = at91_rtc_read_imr() |
|
& (AT91_RTC_ALARM|AT91_RTC_SECEV); |
|
if (at91_rtc_imr) { |
|
if (device_may_wakeup(dev)) { |
|
unsigned long flags; |
|
|
|
enable_irq_wake(irq); |
|
|
|
spin_lock_irqsave(&suspended_lock, flags); |
|
suspended = true; |
|
spin_unlock_irqrestore(&suspended_lock, flags); |
|
} else { |
|
at91_rtc_write_idr(at91_rtc_imr); |
|
} |
|
} |
|
return 0; |
|
} |
|
|
|
static int at91_rtc_resume(struct device *dev) |
|
{ |
|
struct rtc_device *rtc = dev_get_drvdata(dev); |
|
|
|
if (at91_rtc_imr) { |
|
if (device_may_wakeup(dev)) { |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&suspended_lock, flags); |
|
|
|
if (cached_events) { |
|
rtc_update_irq(rtc, 1, cached_events); |
|
cached_events = 0; |
|
} |
|
|
|
suspended = false; |
|
spin_unlock_irqrestore(&suspended_lock, flags); |
|
|
|
disable_irq_wake(irq); |
|
} |
|
at91_rtc_write_ier(at91_rtc_imr); |
|
} |
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume); |
|
|
|
static struct platform_driver at91_rtc_driver = { |
|
.remove = __exit_p(at91_rtc_remove), |
|
.shutdown = at91_rtc_shutdown, |
|
.driver = { |
|
.name = "at91_rtc", |
|
.pm = &at91_rtc_pm_ops, |
|
.of_match_table = of_match_ptr(at91_rtc_dt_ids), |
|
}, |
|
}; |
|
|
|
module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe); |
|
|
|
MODULE_AUTHOR("Rick Bronson"); |
|
MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:at91_rtc");
|
|
|