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466 lines
13 KiB
466 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver |
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* |
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* Copyright (c) 2015 Ariel D'Alessandro <[email protected]> |
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* |
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* Notes |
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* ===== |
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* NXP LPC18xx provides a State Configurable Timer (SCT) which can be configured |
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* as a Pulse Width Modulator. |
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* |
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* SCT supports 16 outputs, 16 events and 16 registers. Each event will be |
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* triggered when its related register matches the SCT counter value, and it |
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* will set or clear a selected output. |
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* |
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* One of the events is preselected to generate the period, thus the maximum |
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* number of simultaneous channels is limited to 15. Notice that period is |
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* global to all the channels, thus PWM driver will refuse setting different |
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* values to it, unless there's only one channel requested. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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|
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/* LPC18xx SCT registers */ |
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#define LPC18XX_PWM_CONFIG 0x000 |
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#define LPC18XX_PWM_CONFIG_UNIFY BIT(0) |
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#define LPC18XX_PWM_CONFIG_NORELOAD BIT(7) |
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#define LPC18XX_PWM_CTRL 0x004 |
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#define LPC18XX_PWM_CTRL_HALT BIT(2) |
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#define LPC18XX_PWM_BIDIR BIT(4) |
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#define LPC18XX_PWM_PRE_SHIFT 5 |
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#define LPC18XX_PWM_PRE_MASK (0xff << LPC18XX_PWM_PRE_SHIFT) |
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#define LPC18XX_PWM_PRE(x) (x << LPC18XX_PWM_PRE_SHIFT) |
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#define LPC18XX_PWM_LIMIT 0x008 |
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#define LPC18XX_PWM_RES_BASE 0x058 |
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#define LPC18XX_PWM_RES_SHIFT(_ch) (_ch * 2) |
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#define LPC18XX_PWM_RES(_ch, _action) (_action << LPC18XX_PWM_RES_SHIFT(_ch)) |
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#define LPC18XX_PWM_RES_MASK(_ch) (0x3 << LPC18XX_PWM_RES_SHIFT(_ch)) |
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#define LPC18XX_PWM_MATCH_BASE 0x100 |
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#define LPC18XX_PWM_MATCH(_ch) (LPC18XX_PWM_MATCH_BASE + _ch * 4) |
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#define LPC18XX_PWM_MATCHREL_BASE 0x200 |
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#define LPC18XX_PWM_MATCHREL(_ch) (LPC18XX_PWM_MATCHREL_BASE + _ch * 4) |
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#define LPC18XX_PWM_EVSTATEMSK_BASE 0x300 |
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#define LPC18XX_PWM_EVSTATEMSK(_ch) (LPC18XX_PWM_EVSTATEMSK_BASE + _ch * 8) |
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#define LPC18XX_PWM_EVSTATEMSK_ALL 0xffffffff |
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#define LPC18XX_PWM_EVCTRL_BASE 0x304 |
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#define LPC18XX_PWM_EVCTRL(_ev) (LPC18XX_PWM_EVCTRL_BASE + _ev * 8) |
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#define LPC18XX_PWM_EVCTRL_MATCH(_ch) _ch |
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#define LPC18XX_PWM_EVCTRL_COMB_SHIFT 12 |
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#define LPC18XX_PWM_EVCTRL_COMB_MATCH (0x1 << LPC18XX_PWM_EVCTRL_COMB_SHIFT) |
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#define LPC18XX_PWM_OUTPUTSET_BASE 0x500 |
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#define LPC18XX_PWM_OUTPUTSET(_ch) (LPC18XX_PWM_OUTPUTSET_BASE + _ch * 8) |
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#define LPC18XX_PWM_OUTPUTCL_BASE 0x504 |
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#define LPC18XX_PWM_OUTPUTCL(_ch) (LPC18XX_PWM_OUTPUTCL_BASE + _ch * 8) |
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/* LPC18xx SCT unified counter */ |
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#define LPC18XX_PWM_TIMER_MAX 0xffffffff |
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/* LPC18xx SCT events */ |
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#define LPC18XX_PWM_EVENT_PERIOD 0 |
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#define LPC18XX_PWM_EVENT_MAX 16 |
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/* SCT conflict resolution */ |
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enum lpc18xx_pwm_res_action { |
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LPC18XX_PWM_RES_NONE, |
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LPC18XX_PWM_RES_SET, |
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LPC18XX_PWM_RES_CLEAR, |
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LPC18XX_PWM_RES_TOGGLE, |
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}; |
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struct lpc18xx_pwm_data { |
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unsigned int duty_event; |
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}; |
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struct lpc18xx_pwm_chip { |
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struct device *dev; |
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struct pwm_chip chip; |
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void __iomem *base; |
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struct clk *pwm_clk; |
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unsigned long clk_rate; |
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unsigned int period_ns; |
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unsigned int min_period_ns; |
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unsigned int max_period_ns; |
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unsigned int period_event; |
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unsigned long event_map; |
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struct mutex res_lock; |
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struct mutex period_lock; |
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}; |
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static inline struct lpc18xx_pwm_chip * |
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to_lpc18xx_pwm_chip(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct lpc18xx_pwm_chip, chip); |
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} |
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static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm, |
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u32 reg, u32 val) |
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{ |
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writel(val, lpc18xx_pwm->base + reg); |
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} |
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static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm, |
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u32 reg) |
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{ |
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return readl(lpc18xx_pwm->base + reg); |
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} |
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static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm, |
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struct pwm_device *pwm, |
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enum lpc18xx_pwm_res_action action) |
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{ |
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u32 val; |
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mutex_lock(&lpc18xx_pwm->res_lock); |
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|
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/* |
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* Simultaneous set and clear may happen on an output, that is the case |
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* when duty_ns == period_ns. LPC18xx SCT allows to set a conflict |
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* resolution action to be taken in such a case. |
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*/ |
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val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE); |
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val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm); |
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val |= LPC18XX_PWM_RES(pwm->hwpwm, action); |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val); |
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mutex_unlock(&lpc18xx_pwm->res_lock); |
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} |
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static void lpc18xx_pwm_config_period(struct pwm_chip *chip, int period_ns) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); |
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u64 val; |
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val = (u64)period_ns * lpc18xx_pwm->clk_rate; |
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do_div(val, NSEC_PER_SEC); |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event), |
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(u32)val - 1); |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event), |
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(u32)val - 1); |
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} |
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static void lpc18xx_pwm_config_duty(struct pwm_chip *chip, |
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struct pwm_device *pwm, int duty_ns) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); |
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struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); |
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u64 val; |
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val = (u64)duty_ns * lpc18xx_pwm->clk_rate; |
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do_div(val, NSEC_PER_SEC); |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_MATCH(lpc18xx_data->duty_event), |
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(u32)val); |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_MATCHREL(lpc18xx_data->duty_event), |
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(u32)val); |
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} |
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static int lpc18xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
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int duty_ns, int period_ns) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); |
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int requested_events, i; |
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if (period_ns < lpc18xx_pwm->min_period_ns || |
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period_ns > lpc18xx_pwm->max_period_ns) { |
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dev_err(chip->dev, "period %d not in range\n", period_ns); |
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return -ERANGE; |
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} |
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mutex_lock(&lpc18xx_pwm->period_lock); |
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requested_events = bitmap_weight(&lpc18xx_pwm->event_map, |
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LPC18XX_PWM_EVENT_MAX); |
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/* |
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* The PWM supports only a single period for all PWM channels. |
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* Once the period is set, it can only be changed if no more than one |
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* channel is requested at that moment. |
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*/ |
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if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns && |
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lpc18xx_pwm->period_ns) { |
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dev_err(chip->dev, "conflicting period requested for PWM %u\n", |
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pwm->hwpwm); |
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mutex_unlock(&lpc18xx_pwm->period_lock); |
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return -EBUSY; |
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} |
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if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) || |
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!lpc18xx_pwm->period_ns) { |
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lpc18xx_pwm->period_ns = period_ns; |
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for (i = 0; i < chip->npwm; i++) |
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pwm_set_period(&chip->pwms[i], period_ns); |
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lpc18xx_pwm_config_period(chip, period_ns); |
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} |
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mutex_unlock(&lpc18xx_pwm->period_lock); |
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lpc18xx_pwm_config_duty(chip, pwm, duty_ns); |
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return 0; |
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} |
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static int lpc18xx_pwm_set_polarity(struct pwm_chip *chip, |
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struct pwm_device *pwm, |
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enum pwm_polarity polarity) |
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{ |
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return 0; |
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} |
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static int lpc18xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); |
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struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); |
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enum lpc18xx_pwm_res_action res_action; |
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unsigned int set_event, clear_event; |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), |
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LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_data->duty_event) | |
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LPC18XX_PWM_EVCTRL_COMB_MATCH); |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_EVSTATEMSK(lpc18xx_data->duty_event), |
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LPC18XX_PWM_EVSTATEMSK_ALL); |
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if (pwm_get_polarity(pwm) == PWM_POLARITY_NORMAL) { |
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set_event = lpc18xx_pwm->period_event; |
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clear_event = lpc18xx_data->duty_event; |
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res_action = LPC18XX_PWM_RES_SET; |
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} else { |
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set_event = lpc18xx_data->duty_event; |
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clear_event = lpc18xx_pwm->period_event; |
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res_action = LPC18XX_PWM_RES_CLEAR; |
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} |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), |
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BIT(set_event)); |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), |
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BIT(clear_event)); |
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lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action); |
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return 0; |
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} |
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static void lpc18xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); |
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struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), 0); |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0); |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0); |
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} |
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static int lpc18xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); |
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struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); |
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unsigned long event; |
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event = find_first_zero_bit(&lpc18xx_pwm->event_map, |
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LPC18XX_PWM_EVENT_MAX); |
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if (event >= LPC18XX_PWM_EVENT_MAX) { |
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dev_err(lpc18xx_pwm->dev, |
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"maximum number of simultaneous channels reached\n"); |
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return -EBUSY; |
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} |
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set_bit(event, &lpc18xx_pwm->event_map); |
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lpc18xx_data->duty_event = event; |
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return 0; |
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} |
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static void lpc18xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); |
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struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); |
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clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map); |
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} |
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static const struct pwm_ops lpc18xx_pwm_ops = { |
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.config = lpc18xx_pwm_config, |
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.set_polarity = lpc18xx_pwm_set_polarity, |
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.enable = lpc18xx_pwm_enable, |
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.disable = lpc18xx_pwm_disable, |
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.request = lpc18xx_pwm_request, |
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.free = lpc18xx_pwm_free, |
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.owner = THIS_MODULE, |
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}; |
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static const struct of_device_id lpc18xx_pwm_of_match[] = { |
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{ .compatible = "nxp,lpc1850-sct-pwm" }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, lpc18xx_pwm_of_match); |
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static int lpc18xx_pwm_probe(struct platform_device *pdev) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm; |
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struct pwm_device *pwm; |
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int ret, i; |
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u64 val; |
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lpc18xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*lpc18xx_pwm), |
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GFP_KERNEL); |
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if (!lpc18xx_pwm) |
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return -ENOMEM; |
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lpc18xx_pwm->dev = &pdev->dev; |
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lpc18xx_pwm->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(lpc18xx_pwm->base)) |
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return PTR_ERR(lpc18xx_pwm->base); |
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lpc18xx_pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm"); |
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if (IS_ERR(lpc18xx_pwm->pwm_clk)) { |
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dev_err(&pdev->dev, "failed to get pwm clock\n"); |
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return PTR_ERR(lpc18xx_pwm->pwm_clk); |
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} |
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ret = clk_prepare_enable(lpc18xx_pwm->pwm_clk); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "could not prepare or enable pwm clock\n"); |
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return ret; |
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} |
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lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk); |
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if (!lpc18xx_pwm->clk_rate) { |
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dev_err(&pdev->dev, "pwm clock has no frequency\n"); |
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ret = -EINVAL; |
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goto disable_pwmclk; |
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} |
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mutex_init(&lpc18xx_pwm->res_lock); |
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mutex_init(&lpc18xx_pwm->period_lock); |
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val = (u64)NSEC_PER_SEC * LPC18XX_PWM_TIMER_MAX; |
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do_div(val, lpc18xx_pwm->clk_rate); |
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lpc18xx_pwm->max_period_ns = val; |
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lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, |
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lpc18xx_pwm->clk_rate); |
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lpc18xx_pwm->chip.dev = &pdev->dev; |
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lpc18xx_pwm->chip.ops = &lpc18xx_pwm_ops; |
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lpc18xx_pwm->chip.base = -1; |
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lpc18xx_pwm->chip.npwm = 16; |
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lpc18xx_pwm->chip.of_xlate = of_pwm_xlate_with_flags; |
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lpc18xx_pwm->chip.of_pwm_n_cells = 3; |
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/* SCT counter must be in unify (32 bit) mode */ |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG, |
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LPC18XX_PWM_CONFIG_UNIFY); |
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|
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/* |
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* Everytime the timer counter reaches the period value, the related |
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* event will be triggered and the counter reset to 0. |
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*/ |
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set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map); |
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lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD; |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event), |
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LPC18XX_PWM_EVSTATEMSK_ALL); |
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val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) | |
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LPC18XX_PWM_EVCTRL_COMB_MATCH; |
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lpc18xx_pwm_writel(lpc18xx_pwm, |
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LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val); |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT, |
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BIT(lpc18xx_pwm->period_event)); |
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ret = pwmchip_add(&lpc18xx_pwm->chip); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret); |
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goto disable_pwmclk; |
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} |
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for (i = 0; i < lpc18xx_pwm->chip.npwm; i++) { |
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struct lpc18xx_pwm_data *data; |
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pwm = &lpc18xx_pwm->chip.pwms[i]; |
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data = devm_kzalloc(lpc18xx_pwm->dev, sizeof(*data), |
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GFP_KERNEL); |
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if (!data) { |
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ret = -ENOMEM; |
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goto remove_pwmchip; |
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} |
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pwm_set_chip_data(pwm, data); |
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} |
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platform_set_drvdata(pdev, lpc18xx_pwm); |
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val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL); |
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val &= ~LPC18XX_PWM_BIDIR; |
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val &= ~LPC18XX_PWM_CTRL_HALT; |
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val &= ~LPC18XX_PWM_PRE_MASK; |
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val |= LPC18XX_PWM_PRE(0); |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val); |
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return 0; |
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remove_pwmchip: |
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pwmchip_remove(&lpc18xx_pwm->chip); |
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disable_pwmclk: |
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clk_disable_unprepare(lpc18xx_pwm->pwm_clk); |
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return ret; |
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} |
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static int lpc18xx_pwm_remove(struct platform_device *pdev) |
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{ |
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struct lpc18xx_pwm_chip *lpc18xx_pwm = platform_get_drvdata(pdev); |
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u32 val; |
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val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL); |
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lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, |
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val | LPC18XX_PWM_CTRL_HALT); |
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clk_disable_unprepare(lpc18xx_pwm->pwm_clk); |
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return pwmchip_remove(&lpc18xx_pwm->chip); |
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} |
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static struct platform_driver lpc18xx_pwm_driver = { |
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.driver = { |
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.name = "lpc18xx-sct-pwm", |
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.of_match_table = lpc18xx_pwm_of_match, |
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}, |
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.probe = lpc18xx_pwm_probe, |
|
.remove = lpc18xx_pwm_remove, |
|
}; |
|
module_platform_driver(lpc18xx_pwm_driver); |
|
|
|
MODULE_AUTHOR("Ariel D'Alessandro <[email protected]>"); |
|
MODULE_DESCRIPTION("NXP LPC18xx PWM driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|