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246 lines
5.8 KiB
246 lines
5.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved. |
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* Copyright (c) 2018-2020, Linaro Limited |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/reset.h> |
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#include <linux/slab.h> |
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#define PHY_CTRL0 0x6C |
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#define PHY_CTRL1 0x70 |
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#define PHY_CTRL2 0x74 |
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#define PHY_CTRL4 0x7C |
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/* PHY_CTRL bits */ |
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#define REF_PHY_EN BIT(0) |
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#define LANE0_PWR_ON BIT(2) |
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#define SWI_PCS_CLK_SEL BIT(4) |
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#define TST_PWR_DOWN BIT(4) |
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#define PHY_RESET BIT(7) |
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#define NUM_BULK_CLKS 3 |
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#define NUM_BULK_REGS 2 |
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struct ssphy_priv { |
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void __iomem *base; |
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struct device *dev; |
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struct reset_control *reset_com; |
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struct reset_control *reset_phy; |
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struct regulator_bulk_data regs[NUM_BULK_REGS]; |
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struct clk_bulk_data clks[NUM_BULK_CLKS]; |
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enum phy_mode mode; |
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}; |
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static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val) |
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{ |
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writel((readl(addr) & ~mask) | val, addr); |
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} |
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static int qcom_ssphy_do_reset(struct ssphy_priv *priv) |
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{ |
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int ret; |
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if (!priv->reset_com) { |
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qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, |
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PHY_RESET); |
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usleep_range(10, 20); |
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qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0); |
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} else { |
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ret = reset_control_assert(priv->reset_com); |
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if (ret) { |
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dev_err(priv->dev, "Failed to assert reset com\n"); |
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return ret; |
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} |
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ret = reset_control_assert(priv->reset_phy); |
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if (ret) { |
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dev_err(priv->dev, "Failed to assert reset phy\n"); |
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return ret; |
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} |
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usleep_range(10, 20); |
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ret = reset_control_deassert(priv->reset_com); |
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if (ret) { |
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dev_err(priv->dev, "Failed to deassert reset com\n"); |
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return ret; |
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} |
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ret = reset_control_deassert(priv->reset_phy); |
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if (ret) { |
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dev_err(priv->dev, "Failed to deassert reset phy\n"); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static int qcom_ssphy_power_on(struct phy *phy) |
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{ |
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struct ssphy_priv *priv = phy_get_drvdata(phy); |
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int ret; |
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ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs); |
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if (ret) |
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return ret; |
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ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks); |
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if (ret) |
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goto err_disable_regulator; |
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ret = qcom_ssphy_do_reset(priv); |
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if (ret) |
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goto err_disable_clock; |
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writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); |
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qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); |
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qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); |
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qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); |
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return 0; |
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err_disable_clock: |
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clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); |
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err_disable_regulator: |
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regulator_bulk_disable(NUM_BULK_REGS, priv->regs); |
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return ret; |
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} |
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static int qcom_ssphy_power_off(struct phy *phy) |
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{ |
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struct ssphy_priv *priv = phy_get_drvdata(phy); |
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qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); |
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qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); |
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qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); |
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clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); |
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regulator_bulk_disable(NUM_BULK_REGS, priv->regs); |
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return 0; |
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} |
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static int qcom_ssphy_init_clock(struct ssphy_priv *priv) |
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{ |
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priv->clks[0].id = "ref"; |
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priv->clks[1].id = "ahb"; |
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priv->clks[2].id = "pipe"; |
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return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks); |
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} |
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static int qcom_ssphy_init_regulator(struct ssphy_priv *priv) |
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{ |
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int ret; |
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priv->regs[0].supply = "vdd"; |
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priv->regs[1].supply = "vdda1p8"; |
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ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs); |
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if (ret) { |
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if (ret != -EPROBE_DEFER) |
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dev_err(priv->dev, "Failed to get regulators\n"); |
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return ret; |
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} |
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return ret; |
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} |
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static int qcom_ssphy_init_reset(struct ssphy_priv *priv) |
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{ |
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priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com"); |
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if (IS_ERR(priv->reset_com)) { |
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dev_err(priv->dev, "Failed to get reset control com\n"); |
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return PTR_ERR(priv->reset_com); |
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} |
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if (priv->reset_com) { |
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/* if reset_com is present, reset_phy is no longer optional */ |
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priv->reset_phy = devm_reset_control_get_exclusive(priv->dev, "phy"); |
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if (IS_ERR(priv->reset_phy)) { |
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dev_err(priv->dev, "Failed to get reset control phy\n"); |
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return PTR_ERR(priv->reset_phy); |
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} |
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} |
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return 0; |
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} |
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static const struct phy_ops qcom_ssphy_ops = { |
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.power_off = qcom_ssphy_power_off, |
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.power_on = qcom_ssphy_power_on, |
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.owner = THIS_MODULE, |
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}; |
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static int qcom_ssphy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct phy_provider *provider; |
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struct ssphy_priv *priv; |
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struct phy *phy; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->dev = dev; |
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priv->mode = PHY_MODE_INVALID; |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) |
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return PTR_ERR(priv->base); |
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ret = qcom_ssphy_init_clock(priv); |
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if (ret) |
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return ret; |
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ret = qcom_ssphy_init_reset(priv); |
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if (ret) |
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return ret; |
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ret = qcom_ssphy_init_regulator(priv); |
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if (ret) |
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return ret; |
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phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops); |
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if (IS_ERR(phy)) { |
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dev_err(dev, "Failed to create the SS phy\n"); |
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return PTR_ERR(phy); |
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} |
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phy_set_drvdata(phy, priv); |
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(provider); |
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} |
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static const struct of_device_id qcom_ssphy_match[] = { |
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{ .compatible = "qcom,usb-ss-28nm-phy", }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, qcom_ssphy_match); |
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static struct platform_driver qcom_ssphy_driver = { |
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.probe = qcom_ssphy_probe, |
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.driver = { |
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.name = "qcom-usb-ssphy", |
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.of_match_table = qcom_ssphy_match, |
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}, |
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}; |
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module_platform_driver(qcom_ssphy_driver); |
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MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver"); |
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MODULE_LICENSE("GPL v2");
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