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346 lines
6.8 KiB
346 lines
6.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (C) 2019-2020 Linaro Ltd. */ |
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#include <linux/log2.h> |
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#include "gsi.h" |
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#include "ipa_data.h" |
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#include "ipa_endpoint.h" |
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#include "ipa_mem.h" |
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/* Endpoint configuration for the SC7180 SoC. */ |
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static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { |
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[IPA_ENDPOINT_AP_COMMAND_TX] = { |
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.ee_id = GSI_EE_AP, |
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.channel_id = 1, |
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.endpoint_id = 6, |
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.toward_ipa = true, |
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.channel = { |
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.tre_count = 256, |
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.event_count = 256, |
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.tlv_count = 20, |
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}, |
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.endpoint = { |
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.seq_type = IPA_SEQ_DMA_ONLY, |
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.config = { |
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.resource_group = 0, |
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.dma_mode = true, |
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.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, |
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}, |
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}, |
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}, |
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[IPA_ENDPOINT_AP_LAN_RX] = { |
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.ee_id = GSI_EE_AP, |
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.channel_id = 2, |
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.endpoint_id = 8, |
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.toward_ipa = false, |
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.channel = { |
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.tre_count = 256, |
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.event_count = 256, |
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.tlv_count = 6, |
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}, |
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.endpoint = { |
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.seq_type = IPA_SEQ_INVALID, |
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.config = { |
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.resource_group = 0, |
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.aggregation = true, |
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.status_enable = true, |
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.rx = { |
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.pad_align = ilog2(sizeof(u32)), |
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}, |
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}, |
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}, |
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}, |
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[IPA_ENDPOINT_AP_MODEM_TX] = { |
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.ee_id = GSI_EE_AP, |
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.channel_id = 0, |
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.endpoint_id = 1, |
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.toward_ipa = true, |
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.channel = { |
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.tre_count = 512, |
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.event_count = 512, |
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.tlv_count = 8, |
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}, |
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.endpoint = { |
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.filter_support = true, |
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.seq_type = |
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IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP, |
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.config = { |
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.resource_group = 0, |
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.checksum = true, |
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.qmap = true, |
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.status_enable = true, |
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.tx = { |
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.status_endpoint = |
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IPA_ENDPOINT_MODEM_AP_RX, |
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}, |
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}, |
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}, |
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}, |
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[IPA_ENDPOINT_AP_MODEM_RX] = { |
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.ee_id = GSI_EE_AP, |
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.channel_id = 3, |
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.endpoint_id = 9, |
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.toward_ipa = false, |
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.channel = { |
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.tre_count = 256, |
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.event_count = 256, |
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.tlv_count = 6, |
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}, |
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.endpoint = { |
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.seq_type = IPA_SEQ_INVALID, |
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.config = { |
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.resource_group = 0, |
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.checksum = true, |
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.qmap = true, |
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.aggregation = true, |
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.rx = { |
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.aggr_close_eof = true, |
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}, |
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}, |
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}, |
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}, |
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[IPA_ENDPOINT_MODEM_COMMAND_TX] = { |
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.ee_id = GSI_EE_MODEM, |
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.channel_id = 1, |
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.endpoint_id = 5, |
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.toward_ipa = true, |
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}, |
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[IPA_ENDPOINT_MODEM_LAN_RX] = { |
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.ee_id = GSI_EE_MODEM, |
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.channel_id = 3, |
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.endpoint_id = 11, |
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.toward_ipa = false, |
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}, |
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[IPA_ENDPOINT_MODEM_AP_TX] = { |
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.ee_id = GSI_EE_MODEM, |
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.channel_id = 0, |
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.endpoint_id = 4, |
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.toward_ipa = true, |
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.endpoint = { |
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.filter_support = true, |
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}, |
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}, |
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[IPA_ENDPOINT_MODEM_AP_RX] = { |
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.ee_id = GSI_EE_MODEM, |
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.channel_id = 2, |
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.endpoint_id = 10, |
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.toward_ipa = false, |
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}, |
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}; |
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/* For the SC7180, resource groups are allocated this way: |
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* group 0: UL_DL |
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*/ |
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static const struct ipa_resource_src ipa_resource_src[] = { |
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{ |
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.type = IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS, |
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.limits[0] = { |
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.min = 3, |
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.max = 63, |
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}, |
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}, |
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{ |
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.type = IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, |
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.limits[0] = { |
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.min = 3, |
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.max = 3, |
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}, |
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}, |
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{ |
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.type = IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, |
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.limits[0] = { |
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.min = 10, |
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.max = 10, |
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}, |
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}, |
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{ |
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.type = IPA_RESOURCE_TYPE_SRC_HPS_DMARS, |
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.limits[0] = { |
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.min = 1, |
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.max = 1, |
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}, |
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}, |
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{ |
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.type = IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, |
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.limits[0] = { |
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.min = 5, |
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.max = 5, |
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}, |
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}, |
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}; |
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static const struct ipa_resource_dst ipa_resource_dst[] = { |
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{ |
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.type = IPA_RESOURCE_TYPE_DST_DATA_SECTORS, |
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.limits[0] = { |
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.min = 3, |
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.max = 3, |
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}, |
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}, |
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{ |
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.type = IPA_RESOURCE_TYPE_DST_DPS_DMARS, |
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.limits[0] = { |
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.min = 1, |
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.max = 63, |
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}, |
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}, |
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}; |
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/* Resource configuration for the SC7180 SoC. */ |
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static const struct ipa_resource_data ipa_resource_data = { |
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.resource_src_count = ARRAY_SIZE(ipa_resource_src), |
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.resource_src = ipa_resource_src, |
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.resource_dst_count = ARRAY_SIZE(ipa_resource_dst), |
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.resource_dst = ipa_resource_dst, |
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}; |
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/* IPA-resident memory region configuration for the SC7180 SoC. */ |
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static const struct ipa_mem ipa_mem_local_data[] = { |
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[IPA_MEM_UC_SHARED] = { |
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.offset = 0x0000, |
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.size = 0x0080, |
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.canary_count = 0, |
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}, |
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[IPA_MEM_UC_INFO] = { |
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.offset = 0x0080, |
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.size = 0x0200, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_V4_FILTER_HASHED] = { |
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.offset = 0x0288, |
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.size = 0, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_V4_FILTER] = { |
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.offset = 0x0290, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_V6_FILTER_HASHED] = { |
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.offset = 0x0310, |
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.size = 0, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_V6_FILTER] = { |
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.offset = 0x0318, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_V4_ROUTE_HASHED] = { |
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.offset = 0x0398, |
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.size = 0, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_V4_ROUTE] = { |
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.offset = 0x03a0, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_V6_ROUTE_HASHED] = { |
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.offset = 0x0420, |
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.size = 0, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_V6_ROUTE] = { |
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.offset = 0x0428, |
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.size = 0x0078, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_MODEM_HEADER] = { |
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.offset = 0x04a8, |
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.size = 0x0140, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_AP_HEADER] = { |
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.offset = 0x05e8, |
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.size = 0x0000, |
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.canary_count = 0, |
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}, |
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[IPA_MEM_MODEM_PROC_CTX] = { |
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.offset = 0x05f0, |
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.size = 0x0200, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_AP_PROC_CTX] = { |
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.offset = 0x07f0, |
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.size = 0x0200, |
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.canary_count = 0, |
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}, |
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[IPA_MEM_PDN_CONFIG] = { |
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.offset = 0x09f8, |
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.size = 0x0050, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_STATS_QUOTA] = { |
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.offset = 0x0a50, |
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.size = 0x0060, |
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.canary_count = 2, |
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}, |
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[IPA_MEM_STATS_TETHERING] = { |
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.offset = 0x0ab0, |
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.size = 0x0140, |
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.canary_count = 0, |
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}, |
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[IPA_MEM_STATS_DROP] = { |
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.offset = 0x0bf0, |
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.size = 0, |
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.canary_count = 0, |
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}, |
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[IPA_MEM_MODEM] = { |
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.offset = 0x0bf0, |
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.size = 0x140c, |
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.canary_count = 0, |
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}, |
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[IPA_MEM_UC_EVENT_RING] = { |
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.offset = 0x2000, |
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.size = 0, |
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.canary_count = 1, |
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}, |
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}; |
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static struct ipa_mem_data ipa_mem_data = { |
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.local_count = ARRAY_SIZE(ipa_mem_local_data), |
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.local = ipa_mem_local_data, |
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.imem_addr = 0x146a8000, |
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.imem_size = 0x00002000, |
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.smem_id = 497, |
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.smem_size = 0x00002000, |
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}; |
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/* Interconnect bandwidths are in 1000 byte/second units */ |
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static struct ipa_interconnect_data ipa_interconnect_data[] = { |
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{ |
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.name = "memory", |
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.peak_bandwidth = 465000, /* 465 MBps */ |
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.average_bandwidth = 80000, /* 80 MBps */ |
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}, |
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/* Average bandwidth is unused for the next two interconnects */ |
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{ |
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.name = "imem", |
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.peak_bandwidth = 68570, /* 68.570 MBps */ |
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.average_bandwidth = 0, /* unused */ |
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}, |
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{ |
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.name = "config", |
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.peak_bandwidth = 30000, /* 30 MBps */ |
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.average_bandwidth = 0, /* unused */ |
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}, |
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}; |
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static struct ipa_clock_data ipa_clock_data = { |
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.core_clock_rate = 100 * 1000 * 1000, /* Hz */ |
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.interconnect_count = ARRAY_SIZE(ipa_interconnect_data), |
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.interconnect_data = ipa_interconnect_data, |
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}; |
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/* Configuration data for the SC7180 SoC. */ |
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const struct ipa_data ipa_data_sc7180 = { |
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.version = IPA_VERSION_4_2, |
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.endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), |
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.endpoint_data = ipa_gsi_endpoint_data, |
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.resource_data = &ipa_resource_data, |
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.mem_data = &ipa_mem_data, |
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.clock_data = &ipa_clock_data, |
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};
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