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113 lines
4.0 KiB
113 lines
4.0 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2005, Intec Automation Inc. |
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* Copyright (C) 2014, Freescale Semiconductor, Inc. |
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*/ |
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#ifndef __LINUX_MTD_SFDP_H |
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#define __LINUX_MTD_SFDP_H |
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/* SFDP revisions */ |
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#define SFDP_JESD216_MAJOR 1 |
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#define SFDP_JESD216_MINOR 0 |
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#define SFDP_JESD216A_MINOR 5 |
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#define SFDP_JESD216B_MINOR 6 |
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/* Basic Flash Parameter Table */ |
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/* |
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* JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. |
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* They are indexed from 1 but C arrays are indexed from 0. |
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*/ |
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#define BFPT_DWORD(i) ((i) - 1) |
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#define BFPT_DWORD_MAX 20 |
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struct sfdp_bfpt { |
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u32 dwords[BFPT_DWORD_MAX]; |
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}; |
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/* The first version of JESD216 defined only 9 DWORDs. */ |
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#define BFPT_DWORD_MAX_JESD216 9 |
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#define BFPT_DWORD_MAX_JESD216B 16 |
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/* 1st DWORD. */ |
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#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) |
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#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) |
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#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) |
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#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) |
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#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) |
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#define BFPT_DWORD1_DTR BIT(19) |
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#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) |
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#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) |
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#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) |
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/* 5th DWORD. */ |
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#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) |
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#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) |
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/* 11th DWORD. */ |
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#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 |
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#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) |
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/* 15th DWORD. */ |
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/* |
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* (from JESD216 rev B) |
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* Quad Enable Requirements (QER): |
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* - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 |
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* reads based on instruction. DQ3/HOLD# functions are hold during |
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* instruction phase. |
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* - 001b: QE is bit 1 of status register 2. It is set via Write Status with |
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* two data bytes where bit 1 of the second byte is one. |
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* [...] |
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* Writing only one byte to the status register has the side-effect of |
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* clearing status register 2, including the QE bit. The 100b code is |
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* used if writing one byte to the status register does not modify |
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* status register 2. |
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* - 010b: QE is bit 6 of status register 1. It is set via Write Status with |
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* one data byte where bit 6 is one. |
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* [...] |
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* - 011b: QE is bit 7 of status register 2. It is set via Write status |
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* register 2 instruction 3Eh with one data byte where bit 7 is one. |
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* [...] |
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* The status register 2 is read using instruction 3Fh. |
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* - 100b: QE is bit 1 of status register 2. It is set via Write Status with |
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* two data bytes where bit 1 of the second byte is one. |
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* [...] |
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* In contrast to the 001b code, writing one byte to the status |
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* register does not modify status register 2. |
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* - 101b: QE is bit 1 of status register 2. Status register 1 is read using |
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* Read Status instruction 05h. Status register2 is read using |
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* instruction 35h. QE is set via Write Status instruction 01h with |
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* two data bytes where bit 1 of the second byte is one. |
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* [...] |
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*/ |
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#define BFPT_DWORD15_QER_MASK GENMASK(22, 20) |
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#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ |
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#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) |
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#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ |
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#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) |
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#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) |
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#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ |
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#define BFPT_DWORD16_SWRST_EN_RST BIT(12) |
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#define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) |
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#define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ |
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#define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ |
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#define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ |
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#define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ |
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struct sfdp_parameter_header { |
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u8 id_lsb; |
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u8 minor; |
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u8 major; |
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u8 length; /* in double words */ |
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u8 parameter_table_pointer[3]; /* byte address */ |
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u8 id_msb; |
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}; |
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int spi_nor_parse_sfdp(struct spi_nor *nor, |
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struct spi_nor_flash_parameter *params); |
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#endif /* __LINUX_MTD_SFDP_H */
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