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486 lines
11 KiB
486 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* SPI NOR driver for NXP SPI Flash Interface (SPIFI) |
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* |
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* Copyright (C) 2015 Joachim Eastwood <[email protected]> |
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* |
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* Based on Freescale QuadSPI driver: |
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* Copyright (C) 2013 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/mtd/spi-nor.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/spi/spi.h> |
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/* NXP SPIFI registers, bits and macros */ |
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#define SPIFI_CTRL 0x000 |
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#define SPIFI_CTRL_TIMEOUT(timeout) (timeout) |
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#define SPIFI_CTRL_CSHIGH(cshigh) ((cshigh) << 16) |
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#define SPIFI_CTRL_MODE3 BIT(23) |
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#define SPIFI_CTRL_DUAL BIT(28) |
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#define SPIFI_CTRL_FBCLK BIT(30) |
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#define SPIFI_CMD 0x004 |
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#define SPIFI_CMD_DATALEN(dlen) ((dlen) & 0x3fff) |
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#define SPIFI_CMD_DOUT BIT(15) |
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#define SPIFI_CMD_INTLEN(ilen) ((ilen) << 16) |
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#define SPIFI_CMD_FIELDFORM(field) ((field) << 19) |
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#define SPIFI_CMD_FIELDFORM_ALL_SERIAL SPIFI_CMD_FIELDFORM(0x0) |
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#define SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA SPIFI_CMD_FIELDFORM(0x1) |
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#define SPIFI_CMD_FRAMEFORM(frame) ((frame) << 21) |
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#define SPIFI_CMD_FRAMEFORM_OPCODE_ONLY SPIFI_CMD_FRAMEFORM(0x1) |
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#define SPIFI_CMD_OPCODE(op) ((op) << 24) |
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#define SPIFI_ADDR 0x008 |
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#define SPIFI_IDATA 0x00c |
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#define SPIFI_CLIMIT 0x010 |
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#define SPIFI_DATA 0x014 |
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#define SPIFI_MCMD 0x018 |
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#define SPIFI_STAT 0x01c |
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#define SPIFI_STAT_MCINIT BIT(0) |
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#define SPIFI_STAT_CMD BIT(1) |
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#define SPIFI_STAT_RESET BIT(4) |
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#define SPI_NOR_MAX_ID_LEN 6 |
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struct nxp_spifi { |
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struct device *dev; |
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struct clk *clk_spifi; |
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struct clk *clk_reg; |
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void __iomem *io_base; |
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void __iomem *flash_base; |
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struct spi_nor nor; |
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bool memory_mode; |
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u32 mcmd; |
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}; |
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static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi) |
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{ |
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u8 stat; |
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int ret; |
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ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, |
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!(stat & SPIFI_STAT_CMD), 10, 30); |
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if (ret) |
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dev_warn(spifi->dev, "command timed out\n"); |
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return ret; |
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} |
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static int nxp_spifi_reset(struct nxp_spifi *spifi) |
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{ |
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u8 stat; |
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int ret; |
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writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); |
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ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, |
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!(stat & SPIFI_STAT_RESET), 10, 30); |
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if (ret) |
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dev_warn(spifi->dev, "state reset timed out\n"); |
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return ret; |
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} |
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static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi) |
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{ |
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int ret; |
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if (!spifi->memory_mode) |
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return 0; |
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ret = nxp_spifi_reset(spifi); |
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if (ret) |
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dev_err(spifi->dev, "unable to enter command mode\n"); |
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else |
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spifi->memory_mode = false; |
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return ret; |
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} |
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static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi) |
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{ |
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u8 stat; |
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int ret; |
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if (spifi->memory_mode) |
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return 0; |
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writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD); |
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ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, |
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stat & SPIFI_STAT_MCINIT, 10, 30); |
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if (ret) |
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dev_err(spifi->dev, "unable to enter memory mode\n"); |
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else |
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spifi->memory_mode = true; |
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return ret; |
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} |
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static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, |
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size_t len) |
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{ |
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struct nxp_spifi *spifi = nor->priv; |
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u32 cmd; |
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int ret; |
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ret = nxp_spifi_set_memory_mode_off(spifi); |
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if (ret) |
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return ret; |
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cmd = SPIFI_CMD_DATALEN(len) | |
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SPIFI_CMD_OPCODE(opcode) | |
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SPIFI_CMD_FIELDFORM_ALL_SERIAL | |
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SPIFI_CMD_FRAMEFORM_OPCODE_ONLY; |
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writel(cmd, spifi->io_base + SPIFI_CMD); |
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while (len--) |
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*buf++ = readb(spifi->io_base + SPIFI_DATA); |
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return nxp_spifi_wait_for_cmd(spifi); |
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} |
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static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf, |
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size_t len) |
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{ |
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struct nxp_spifi *spifi = nor->priv; |
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u32 cmd; |
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int ret; |
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ret = nxp_spifi_set_memory_mode_off(spifi); |
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if (ret) |
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return ret; |
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cmd = SPIFI_CMD_DOUT | |
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SPIFI_CMD_DATALEN(len) | |
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SPIFI_CMD_OPCODE(opcode) | |
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SPIFI_CMD_FIELDFORM_ALL_SERIAL | |
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SPIFI_CMD_FRAMEFORM_OPCODE_ONLY; |
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writel(cmd, spifi->io_base + SPIFI_CMD); |
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while (len--) |
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writeb(*buf++, spifi->io_base + SPIFI_DATA); |
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return nxp_spifi_wait_for_cmd(spifi); |
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} |
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static ssize_t nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len, |
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u_char *buf) |
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{ |
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struct nxp_spifi *spifi = nor->priv; |
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int ret; |
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ret = nxp_spifi_set_memory_mode_on(spifi); |
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if (ret) |
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return ret; |
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memcpy_fromio(buf, spifi->flash_base + from, len); |
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return len; |
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} |
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static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len, |
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const u_char *buf) |
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{ |
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struct nxp_spifi *spifi = nor->priv; |
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u32 cmd; |
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int ret; |
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size_t i; |
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ret = nxp_spifi_set_memory_mode_off(spifi); |
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if (ret) |
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return ret; |
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writel(to, spifi->io_base + SPIFI_ADDR); |
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cmd = SPIFI_CMD_DOUT | |
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SPIFI_CMD_DATALEN(len) | |
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SPIFI_CMD_FIELDFORM_ALL_SERIAL | |
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SPIFI_CMD_OPCODE(nor->program_opcode) | |
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SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1); |
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writel(cmd, spifi->io_base + SPIFI_CMD); |
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for (i = 0; i < len; i++) |
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writeb(buf[i], spifi->io_base + SPIFI_DATA); |
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ret = nxp_spifi_wait_for_cmd(spifi); |
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if (ret) |
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return ret; |
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return len; |
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} |
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static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs) |
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{ |
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struct nxp_spifi *spifi = nor->priv; |
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u32 cmd; |
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int ret; |
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ret = nxp_spifi_set_memory_mode_off(spifi); |
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if (ret) |
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return ret; |
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writel(offs, spifi->io_base + SPIFI_ADDR); |
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cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL | |
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SPIFI_CMD_OPCODE(nor->erase_opcode) | |
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SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1); |
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writel(cmd, spifi->io_base + SPIFI_CMD); |
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return nxp_spifi_wait_for_cmd(spifi); |
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} |
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static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi) |
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{ |
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switch (spifi->nor.read_proto) { |
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case SNOR_PROTO_1_1_1: |
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spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL; |
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break; |
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case SNOR_PROTO_1_1_2: |
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case SNOR_PROTO_1_1_4: |
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spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA; |
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break; |
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default: |
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dev_err(spifi->dev, "unsupported SPI read mode\n"); |
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return -EINVAL; |
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} |
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/* Memory mode supports address length between 1 and 4 */ |
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if (spifi->nor.addr_width < 1 || spifi->nor.addr_width > 4) |
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return -EINVAL; |
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spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) | |
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SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) | |
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SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1); |
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return 0; |
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} |
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static void nxp_spifi_dummy_id_read(struct spi_nor *nor) |
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{ |
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u8 id[SPI_NOR_MAX_ID_LEN]; |
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nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, |
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SPI_NOR_MAX_ID_LEN); |
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} |
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static const struct spi_nor_controller_ops nxp_spifi_controller_ops = { |
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.read_reg = nxp_spifi_read_reg, |
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.write_reg = nxp_spifi_write_reg, |
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.read = nxp_spifi_read, |
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.write = nxp_spifi_write, |
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.erase = nxp_spifi_erase, |
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}; |
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static int nxp_spifi_setup_flash(struct nxp_spifi *spifi, |
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struct device_node *np) |
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{ |
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struct spi_nor_hwcaps hwcaps = { |
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.mask = SNOR_HWCAPS_READ | |
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SNOR_HWCAPS_READ_FAST | |
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SNOR_HWCAPS_PP, |
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}; |
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u32 ctrl, property; |
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u16 mode = 0; |
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int ret; |
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if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) { |
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switch (property) { |
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case 1: |
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break; |
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case 2: |
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mode |= SPI_RX_DUAL; |
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break; |
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case 4: |
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mode |= SPI_RX_QUAD; |
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break; |
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default: |
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dev_err(spifi->dev, "unsupported rx-bus-width\n"); |
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return -EINVAL; |
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} |
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} |
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if (of_find_property(np, "spi-cpha", NULL)) |
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mode |= SPI_CPHA; |
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if (of_find_property(np, "spi-cpol", NULL)) |
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mode |= SPI_CPOL; |
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/* Setup control register defaults */ |
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ctrl = SPIFI_CTRL_TIMEOUT(1000) | |
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SPIFI_CTRL_CSHIGH(15) | |
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SPIFI_CTRL_FBCLK; |
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if (mode & SPI_RX_DUAL) { |
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ctrl |= SPIFI_CTRL_DUAL; |
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; |
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} else if (mode & SPI_RX_QUAD) { |
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ctrl &= ~SPIFI_CTRL_DUAL; |
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; |
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} else { |
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ctrl |= SPIFI_CTRL_DUAL; |
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} |
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switch (mode & (SPI_CPHA | SPI_CPOL)) { |
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case SPI_MODE_0: |
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ctrl &= ~SPIFI_CTRL_MODE3; |
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break; |
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case SPI_MODE_3: |
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ctrl |= SPIFI_CTRL_MODE3; |
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break; |
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default: |
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dev_err(spifi->dev, "only mode 0 and 3 supported\n"); |
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return -EINVAL; |
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} |
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writel(ctrl, spifi->io_base + SPIFI_CTRL); |
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spifi->nor.dev = spifi->dev; |
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spi_nor_set_flash_node(&spifi->nor, np); |
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spifi->nor.priv = spifi; |
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spifi->nor.controller_ops = &nxp_spifi_controller_ops; |
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/* |
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* The first read on a hard reset isn't reliable so do a |
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* dummy read of the id before calling spi_nor_scan(). |
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* The reason for this problem is unknown. |
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* |
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* The official NXP spifilib uses more or less the same |
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* workaround that is applied here by reading the device |
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* id multiple times. |
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*/ |
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nxp_spifi_dummy_id_read(&spifi->nor); |
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ret = spi_nor_scan(&spifi->nor, NULL, &hwcaps); |
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if (ret) { |
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dev_err(spifi->dev, "device scan failed\n"); |
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return ret; |
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} |
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ret = nxp_spifi_setup_memory_cmd(spifi); |
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if (ret) { |
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dev_err(spifi->dev, "memory command setup failed\n"); |
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return ret; |
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} |
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ret = mtd_device_register(&spifi->nor.mtd, NULL, 0); |
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if (ret) { |
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dev_err(spifi->dev, "mtd device parse failed\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int nxp_spifi_probe(struct platform_device *pdev) |
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{ |
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struct device_node *flash_np; |
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struct nxp_spifi *spifi; |
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struct resource *res; |
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int ret; |
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spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL); |
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if (!spifi) |
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return -ENOMEM; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spifi"); |
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spifi->io_base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(spifi->io_base)) |
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return PTR_ERR(spifi->io_base); |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash"); |
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spifi->flash_base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(spifi->flash_base)) |
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return PTR_ERR(spifi->flash_base); |
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spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi"); |
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if (IS_ERR(spifi->clk_spifi)) { |
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dev_err(&pdev->dev, "spifi clock not found\n"); |
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return PTR_ERR(spifi->clk_spifi); |
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} |
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spifi->clk_reg = devm_clk_get(&pdev->dev, "reg"); |
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if (IS_ERR(spifi->clk_reg)) { |
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dev_err(&pdev->dev, "reg clock not found\n"); |
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return PTR_ERR(spifi->clk_reg); |
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} |
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ret = clk_prepare_enable(spifi->clk_reg); |
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if (ret) { |
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dev_err(&pdev->dev, "unable to enable reg clock\n"); |
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return ret; |
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} |
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ret = clk_prepare_enable(spifi->clk_spifi); |
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if (ret) { |
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dev_err(&pdev->dev, "unable to enable spifi clock\n"); |
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goto dis_clk_reg; |
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} |
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spifi->dev = &pdev->dev; |
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platform_set_drvdata(pdev, spifi); |
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/* Initialize and reset device */ |
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nxp_spifi_reset(spifi); |
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writel(0, spifi->io_base + SPIFI_IDATA); |
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writel(0, spifi->io_base + SPIFI_MCMD); |
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nxp_spifi_reset(spifi); |
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flash_np = of_get_next_available_child(pdev->dev.of_node, NULL); |
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if (!flash_np) { |
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dev_err(&pdev->dev, "no SPI flash device to configure\n"); |
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ret = -ENODEV; |
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goto dis_clks; |
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} |
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ret = nxp_spifi_setup_flash(spifi, flash_np); |
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of_node_put(flash_np); |
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if (ret) { |
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dev_err(&pdev->dev, "unable to setup flash chip\n"); |
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goto dis_clks; |
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} |
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return 0; |
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dis_clks: |
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clk_disable_unprepare(spifi->clk_spifi); |
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dis_clk_reg: |
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clk_disable_unprepare(spifi->clk_reg); |
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return ret; |
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} |
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static int nxp_spifi_remove(struct platform_device *pdev) |
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{ |
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struct nxp_spifi *spifi = platform_get_drvdata(pdev); |
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mtd_device_unregister(&spifi->nor.mtd); |
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clk_disable_unprepare(spifi->clk_spifi); |
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clk_disable_unprepare(spifi->clk_reg); |
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return 0; |
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} |
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static const struct of_device_id nxp_spifi_match[] = { |
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{.compatible = "nxp,lpc1773-spifi"}, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, nxp_spifi_match); |
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static struct platform_driver nxp_spifi_driver = { |
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.probe = nxp_spifi_probe, |
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.remove = nxp_spifi_remove, |
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.driver = { |
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.name = "nxp-spifi", |
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.of_match_table = nxp_spifi_match, |
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}, |
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}; |
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module_platform_driver(nxp_spifi_driver); |
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MODULE_DESCRIPTION("NXP SPI Flash Interface driver"); |
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MODULE_AUTHOR("Joachim Eastwood <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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