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501 lines
12 KiB
501 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* HiSilicon FMC SPI NOR flash controller driver |
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* |
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* Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/spi-nor.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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/* Hardware register offsets and field definitions */ |
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#define FMC_CFG 0x00 |
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#define FMC_CFG_OP_MODE_MASK BIT_MASK(0) |
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#define FMC_CFG_OP_MODE_BOOT 0 |
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#define FMC_CFG_OP_MODE_NORMAL 1 |
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#define FMC_CFG_FLASH_SEL(type) (((type) & 0x3) << 1) |
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#define FMC_CFG_FLASH_SEL_MASK 0x6 |
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#define FMC_ECC_TYPE(type) (((type) & 0x7) << 5) |
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#define FMC_ECC_TYPE_MASK GENMASK(7, 5) |
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#define SPI_NOR_ADDR_MODE_MASK BIT_MASK(10) |
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#define SPI_NOR_ADDR_MODE_3BYTES (0x0 << 10) |
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#define SPI_NOR_ADDR_MODE_4BYTES (0x1 << 10) |
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#define FMC_GLOBAL_CFG 0x04 |
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#define FMC_GLOBAL_CFG_WP_ENABLE BIT(6) |
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#define FMC_SPI_TIMING_CFG 0x08 |
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#define TIMING_CFG_TCSH(nr) (((nr) & 0xf) << 8) |
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#define TIMING_CFG_TCSS(nr) (((nr) & 0xf) << 4) |
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#define TIMING_CFG_TSHSL(nr) ((nr) & 0xf) |
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#define CS_HOLD_TIME 0x6 |
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#define CS_SETUP_TIME 0x6 |
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#define CS_DESELECT_TIME 0xf |
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#define FMC_INT 0x18 |
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#define FMC_INT_OP_DONE BIT(0) |
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#define FMC_INT_CLR 0x20 |
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#define FMC_CMD 0x24 |
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#define FMC_CMD_CMD1(cmd) ((cmd) & 0xff) |
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#define FMC_ADDRL 0x2c |
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#define FMC_OP_CFG 0x30 |
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#define OP_CFG_FM_CS(cs) ((cs) << 11) |
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#define OP_CFG_MEM_IF_TYPE(type) (((type) & 0x7) << 7) |
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#define OP_CFG_ADDR_NUM(addr) (((addr) & 0x7) << 4) |
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#define OP_CFG_DUMMY_NUM(dummy) ((dummy) & 0xf) |
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#define FMC_DATA_NUM 0x38 |
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#define FMC_DATA_NUM_CNT(cnt) ((cnt) & GENMASK(13, 0)) |
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#define FMC_OP 0x3c |
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#define FMC_OP_DUMMY_EN BIT(8) |
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#define FMC_OP_CMD1_EN BIT(7) |
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#define FMC_OP_ADDR_EN BIT(6) |
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#define FMC_OP_WRITE_DATA_EN BIT(5) |
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#define FMC_OP_READ_DATA_EN BIT(2) |
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#define FMC_OP_READ_STATUS_EN BIT(1) |
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#define FMC_OP_REG_OP_START BIT(0) |
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#define FMC_DMA_LEN 0x40 |
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#define FMC_DMA_LEN_SET(len) ((len) & GENMASK(27, 0)) |
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#define FMC_DMA_SADDR_D0 0x4c |
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#define HIFMC_DMA_MAX_LEN (4096) |
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#define HIFMC_DMA_MASK (HIFMC_DMA_MAX_LEN - 1) |
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#define FMC_OP_DMA 0x68 |
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#define OP_CTRL_RD_OPCODE(code) (((code) & 0xff) << 16) |
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#define OP_CTRL_WR_OPCODE(code) (((code) & 0xff) << 8) |
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#define OP_CTRL_RW_OP(op) ((op) << 1) |
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#define OP_CTRL_DMA_OP_READY BIT(0) |
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#define FMC_OP_READ 0x0 |
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#define FMC_OP_WRITE 0x1 |
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#define FMC_WAIT_TIMEOUT 1000000 |
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enum hifmc_iftype { |
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IF_TYPE_STD, |
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IF_TYPE_DUAL, |
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IF_TYPE_DIO, |
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IF_TYPE_QUAD, |
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IF_TYPE_QIO, |
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}; |
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struct hifmc_priv { |
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u32 chipselect; |
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u32 clkrate; |
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struct hifmc_host *host; |
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}; |
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#define HIFMC_MAX_CHIP_NUM 2 |
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struct hifmc_host { |
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struct device *dev; |
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struct mutex lock; |
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void __iomem *regbase; |
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void __iomem *iobase; |
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struct clk *clk; |
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void *buffer; |
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dma_addr_t dma_buffer; |
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struct spi_nor *nor[HIFMC_MAX_CHIP_NUM]; |
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u32 num_chip; |
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}; |
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static inline int hisi_spi_nor_wait_op_finish(struct hifmc_host *host) |
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{ |
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u32 reg; |
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return readl_poll_timeout(host->regbase + FMC_INT, reg, |
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(reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT); |
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} |
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static int hisi_spi_nor_get_if_type(enum spi_nor_protocol proto) |
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{ |
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enum hifmc_iftype if_type; |
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switch (proto) { |
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case SNOR_PROTO_1_1_2: |
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if_type = IF_TYPE_DUAL; |
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break; |
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case SNOR_PROTO_1_2_2: |
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if_type = IF_TYPE_DIO; |
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break; |
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case SNOR_PROTO_1_1_4: |
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if_type = IF_TYPE_QUAD; |
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break; |
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case SNOR_PROTO_1_4_4: |
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if_type = IF_TYPE_QIO; |
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break; |
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case SNOR_PROTO_1_1_1: |
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default: |
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if_type = IF_TYPE_STD; |
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break; |
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} |
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return if_type; |
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} |
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static void hisi_spi_nor_init(struct hifmc_host *host) |
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{ |
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u32 reg; |
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reg = TIMING_CFG_TCSH(CS_HOLD_TIME) |
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| TIMING_CFG_TCSS(CS_SETUP_TIME) |
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| TIMING_CFG_TSHSL(CS_DESELECT_TIME); |
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writel(reg, host->regbase + FMC_SPI_TIMING_CFG); |
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} |
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static int hisi_spi_nor_prep(struct spi_nor *nor) |
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{ |
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struct hifmc_priv *priv = nor->priv; |
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struct hifmc_host *host = priv->host; |
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int ret; |
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mutex_lock(&host->lock); |
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ret = clk_set_rate(host->clk, priv->clkrate); |
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if (ret) |
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goto out; |
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ret = clk_prepare_enable(host->clk); |
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if (ret) |
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goto out; |
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return 0; |
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out: |
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mutex_unlock(&host->lock); |
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return ret; |
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} |
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static void hisi_spi_nor_unprep(struct spi_nor *nor) |
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{ |
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struct hifmc_priv *priv = nor->priv; |
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struct hifmc_host *host = priv->host; |
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clk_disable_unprepare(host->clk); |
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mutex_unlock(&host->lock); |
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} |
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static int hisi_spi_nor_op_reg(struct spi_nor *nor, |
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u8 opcode, size_t len, u8 optype) |
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{ |
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struct hifmc_priv *priv = nor->priv; |
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struct hifmc_host *host = priv->host; |
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u32 reg; |
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reg = FMC_CMD_CMD1(opcode); |
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writel(reg, host->regbase + FMC_CMD); |
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reg = FMC_DATA_NUM_CNT(len); |
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writel(reg, host->regbase + FMC_DATA_NUM); |
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reg = OP_CFG_FM_CS(priv->chipselect); |
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writel(reg, host->regbase + FMC_OP_CFG); |
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writel(0xff, host->regbase + FMC_INT_CLR); |
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reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype; |
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writel(reg, host->regbase + FMC_OP); |
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return hisi_spi_nor_wait_op_finish(host); |
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} |
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static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, |
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size_t len) |
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{ |
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struct hifmc_priv *priv = nor->priv; |
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struct hifmc_host *host = priv->host; |
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int ret; |
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ret = hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_READ_DATA_EN); |
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if (ret) |
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return ret; |
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memcpy_fromio(buf, host->iobase, len); |
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return 0; |
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} |
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static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode, |
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const u8 *buf, size_t len) |
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{ |
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struct hifmc_priv *priv = nor->priv; |
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struct hifmc_host *host = priv->host; |
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if (len) |
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memcpy_toio(host->iobase, buf, len); |
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return hisi_spi_nor_op_reg(nor, opcode, len, FMC_OP_WRITE_DATA_EN); |
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} |
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static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off, |
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dma_addr_t dma_buf, size_t len, u8 op_type) |
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{ |
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struct hifmc_priv *priv = nor->priv; |
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struct hifmc_host *host = priv->host; |
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u8 if_type = 0; |
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u32 reg; |
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reg = readl(host->regbase + FMC_CFG); |
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reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK); |
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reg |= FMC_CFG_OP_MODE_NORMAL; |
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reg |= (nor->addr_width == 4) ? SPI_NOR_ADDR_MODE_4BYTES |
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: SPI_NOR_ADDR_MODE_3BYTES; |
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writel(reg, host->regbase + FMC_CFG); |
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writel(start_off, host->regbase + FMC_ADDRL); |
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writel(dma_buf, host->regbase + FMC_DMA_SADDR_D0); |
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writel(FMC_DMA_LEN_SET(len), host->regbase + FMC_DMA_LEN); |
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reg = OP_CFG_FM_CS(priv->chipselect); |
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if (op_type == FMC_OP_READ) |
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if_type = hisi_spi_nor_get_if_type(nor->read_proto); |
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else |
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if_type = hisi_spi_nor_get_if_type(nor->write_proto); |
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reg |= OP_CFG_MEM_IF_TYPE(if_type); |
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if (op_type == FMC_OP_READ) |
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reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3); |
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writel(reg, host->regbase + FMC_OP_CFG); |
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writel(0xff, host->regbase + FMC_INT_CLR); |
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reg = OP_CTRL_RW_OP(op_type) | OP_CTRL_DMA_OP_READY; |
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reg |= (op_type == FMC_OP_READ) |
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? OP_CTRL_RD_OPCODE(nor->read_opcode) |
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: OP_CTRL_WR_OPCODE(nor->program_opcode); |
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writel(reg, host->regbase + FMC_OP_DMA); |
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return hisi_spi_nor_wait_op_finish(host); |
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} |
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static ssize_t hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len, |
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u_char *read_buf) |
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{ |
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struct hifmc_priv *priv = nor->priv; |
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struct hifmc_host *host = priv->host; |
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size_t offset; |
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int ret; |
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for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) { |
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size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset); |
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ret = hisi_spi_nor_dma_transfer(nor, |
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from + offset, host->dma_buffer, trans, FMC_OP_READ); |
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if (ret) { |
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dev_warn(nor->dev, "DMA read timeout\n"); |
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return ret; |
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} |
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memcpy(read_buf + offset, host->buffer, trans); |
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} |
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return len; |
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} |
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static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to, |
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size_t len, const u_char *write_buf) |
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{ |
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struct hifmc_priv *priv = nor->priv; |
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struct hifmc_host *host = priv->host; |
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size_t offset; |
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int ret; |
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for (offset = 0; offset < len; offset += HIFMC_DMA_MAX_LEN) { |
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size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset); |
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memcpy(host->buffer, write_buf + offset, trans); |
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ret = hisi_spi_nor_dma_transfer(nor, |
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to + offset, host->dma_buffer, trans, FMC_OP_WRITE); |
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if (ret) { |
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dev_warn(nor->dev, "DMA write timeout\n"); |
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return ret; |
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} |
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} |
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return len; |
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} |
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static const struct spi_nor_controller_ops hisi_controller_ops = { |
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.prepare = hisi_spi_nor_prep, |
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.unprepare = hisi_spi_nor_unprep, |
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.read_reg = hisi_spi_nor_read_reg, |
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.write_reg = hisi_spi_nor_write_reg, |
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.read = hisi_spi_nor_read, |
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.write = hisi_spi_nor_write, |
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}; |
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/* |
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* Get spi flash device information and register it as a mtd device. |
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*/ |
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static int hisi_spi_nor_register(struct device_node *np, |
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struct hifmc_host *host) |
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{ |
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const struct spi_nor_hwcaps hwcaps = { |
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.mask = SNOR_HWCAPS_READ | |
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SNOR_HWCAPS_READ_FAST | |
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SNOR_HWCAPS_READ_1_1_2 | |
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SNOR_HWCAPS_READ_1_1_4 | |
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SNOR_HWCAPS_PP, |
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}; |
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struct device *dev = host->dev; |
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struct spi_nor *nor; |
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struct hifmc_priv *priv; |
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struct mtd_info *mtd; |
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int ret; |
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nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL); |
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if (!nor) |
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return -ENOMEM; |
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nor->dev = dev; |
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spi_nor_set_flash_node(nor, np); |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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ret = of_property_read_u32(np, "reg", &priv->chipselect); |
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if (ret) { |
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dev_err(dev, "There's no reg property for %pOF\n", |
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np); |
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return ret; |
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} |
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ret = of_property_read_u32(np, "spi-max-frequency", |
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&priv->clkrate); |
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if (ret) { |
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dev_err(dev, "There's no spi-max-frequency property for %pOF\n", |
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np); |
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return ret; |
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} |
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priv->host = host; |
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nor->priv = priv; |
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nor->controller_ops = &hisi_controller_ops; |
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ret = spi_nor_scan(nor, NULL, &hwcaps); |
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if (ret) |
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return ret; |
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mtd = &nor->mtd; |
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mtd->name = np->name; |
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ret = mtd_device_register(mtd, NULL, 0); |
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if (ret) |
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return ret; |
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host->nor[host->num_chip] = nor; |
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host->num_chip++; |
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return 0; |
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} |
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static void hisi_spi_nor_unregister_all(struct hifmc_host *host) |
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{ |
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int i; |
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for (i = 0; i < host->num_chip; i++) |
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mtd_device_unregister(&host->nor[i]->mtd); |
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} |
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static int hisi_spi_nor_register_all(struct hifmc_host *host) |
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{ |
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struct device *dev = host->dev; |
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struct device_node *np; |
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int ret; |
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for_each_available_child_of_node(dev->of_node, np) { |
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ret = hisi_spi_nor_register(np, host); |
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if (ret) { |
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of_node_put(np); |
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goto fail; |
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} |
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if (host->num_chip == HIFMC_MAX_CHIP_NUM) { |
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dev_warn(dev, "Flash device number exceeds the maximum chipselect number\n"); |
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of_node_put(np); |
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break; |
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} |
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} |
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return 0; |
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fail: |
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hisi_spi_nor_unregister_all(host); |
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return ret; |
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} |
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static int hisi_spi_nor_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct resource *res; |
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struct hifmc_host *host; |
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int ret; |
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); |
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if (!host) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, host); |
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host->dev = dev; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); |
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host->regbase = devm_ioremap_resource(dev, res); |
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if (IS_ERR(host->regbase)) |
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return PTR_ERR(host->regbase); |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory"); |
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host->iobase = devm_ioremap_resource(dev, res); |
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if (IS_ERR(host->iobase)) |
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return PTR_ERR(host->iobase); |
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host->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(host->clk)) |
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return PTR_ERR(host->clk); |
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
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if (ret) { |
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dev_warn(dev, "Unable to set dma mask\n"); |
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return ret; |
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} |
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host->buffer = dmam_alloc_coherent(dev, HIFMC_DMA_MAX_LEN, |
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&host->dma_buffer, GFP_KERNEL); |
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if (!host->buffer) |
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return -ENOMEM; |
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ret = clk_prepare_enable(host->clk); |
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if (ret) |
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return ret; |
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mutex_init(&host->lock); |
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hisi_spi_nor_init(host); |
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ret = hisi_spi_nor_register_all(host); |
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if (ret) |
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mutex_destroy(&host->lock); |
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clk_disable_unprepare(host->clk); |
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return ret; |
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} |
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static int hisi_spi_nor_remove(struct platform_device *pdev) |
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{ |
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struct hifmc_host *host = platform_get_drvdata(pdev); |
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hisi_spi_nor_unregister_all(host); |
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mutex_destroy(&host->lock); |
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clk_disable_unprepare(host->clk); |
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return 0; |
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} |
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static const struct of_device_id hisi_spi_nor_dt_ids[] = { |
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{ .compatible = "hisilicon,fmc-spi-nor"}, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, hisi_spi_nor_dt_ids); |
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static struct platform_driver hisi_spi_nor_driver = { |
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.driver = { |
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.name = "hisi-sfc", |
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.of_match_table = hisi_spi_nor_dt_ids, |
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}, |
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.probe = hisi_spi_nor_probe, |
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.remove = hisi_spi_nor_remove, |
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}; |
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module_platform_driver(hisi_spi_nor_driver); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DESCRIPTION("HiSilicon SPI Nor Flash Controller Driver");
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