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910 lines
25 KiB
910 lines
25 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* ASPEED Static Memory Controller driver |
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* |
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* Copyright (c) 2015-2016, IBM Corporation. |
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*/ |
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#include <linux/bug.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/mutex.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/mtd/spi-nor.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/sizes.h> |
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#include <linux/sysfs.h> |
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#define DEVICE_NAME "aspeed-smc" |
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|
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/* |
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* The driver only support SPI flash |
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*/ |
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enum aspeed_smc_flash_type { |
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smc_type_nor = 0, |
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smc_type_nand = 1, |
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smc_type_spi = 2, |
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}; |
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struct aspeed_smc_chip; |
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struct aspeed_smc_info { |
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u32 maxsize; /* maximum size of chip window */ |
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u8 nce; /* number of chip enables */ |
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bool hastype; /* flash type field exists in config reg */ |
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u8 we0; /* shift for write enable bit for CE0 */ |
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u8 ctl0; /* offset in regs of ctl for CE0 */ |
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void (*set_4b)(struct aspeed_smc_chip *chip); |
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}; |
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static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip); |
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static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip); |
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static const struct aspeed_smc_info fmc_2400_info = { |
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.maxsize = 64 * 1024 * 1024, |
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.nce = 5, |
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.hastype = true, |
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.we0 = 16, |
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.ctl0 = 0x10, |
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.set_4b = aspeed_smc_chip_set_4b, |
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}; |
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static const struct aspeed_smc_info spi_2400_info = { |
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.maxsize = 64 * 1024 * 1024, |
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.nce = 1, |
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.hastype = false, |
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.we0 = 0, |
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.ctl0 = 0x04, |
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.set_4b = aspeed_smc_chip_set_4b_spi_2400, |
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}; |
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static const struct aspeed_smc_info fmc_2500_info = { |
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.maxsize = 256 * 1024 * 1024, |
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.nce = 3, |
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.hastype = true, |
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.we0 = 16, |
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.ctl0 = 0x10, |
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.set_4b = aspeed_smc_chip_set_4b, |
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}; |
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static const struct aspeed_smc_info spi_2500_info = { |
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.maxsize = 128 * 1024 * 1024, |
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.nce = 2, |
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.hastype = false, |
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.we0 = 16, |
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.ctl0 = 0x10, |
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.set_4b = aspeed_smc_chip_set_4b, |
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}; |
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enum aspeed_smc_ctl_reg_value { |
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smc_base, /* base value without mode for other commands */ |
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smc_read, /* command reg for (maybe fast) reads */ |
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smc_write, /* command reg for writes */ |
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smc_max, |
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}; |
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struct aspeed_smc_controller; |
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struct aspeed_smc_chip { |
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int cs; |
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struct aspeed_smc_controller *controller; |
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void __iomem *ctl; /* control register */ |
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void __iomem *ahb_base; /* base of chip window */ |
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u32 ahb_window_size; /* chip mapping window size */ |
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u32 ctl_val[smc_max]; /* control settings */ |
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enum aspeed_smc_flash_type type; /* what type of flash */ |
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struct spi_nor nor; |
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}; |
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struct aspeed_smc_controller { |
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struct device *dev; |
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struct mutex mutex; /* controller access mutex */ |
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const struct aspeed_smc_info *info; /* type info of controller */ |
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void __iomem *regs; /* controller registers */ |
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void __iomem *ahb_base; /* per-chip windows resource */ |
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u32 ahb_window_size; /* full mapping window size */ |
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struct aspeed_smc_chip *chips[]; /* pointers to attached chips */ |
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}; |
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/* |
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* SPI Flash Configuration Register (AST2500 SPI) |
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* or |
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* Type setting Register (AST2500 FMC). |
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* CE0 and CE1 can only be of type SPI. CE2 can be of type NOR but the |
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* driver does not support it. |
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*/ |
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#define CONFIG_REG 0x0 |
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#define CONFIG_DISABLE_LEGACY BIT(31) /* 1 */ |
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#define CONFIG_CE2_WRITE BIT(18) |
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#define CONFIG_CE1_WRITE BIT(17) |
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#define CONFIG_CE0_WRITE BIT(16) |
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#define CONFIG_CE2_TYPE BIT(4) /* AST2500 FMC only */ |
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#define CONFIG_CE1_TYPE BIT(2) /* AST2500 FMC only */ |
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#define CONFIG_CE0_TYPE BIT(0) /* AST2500 FMC only */ |
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/* |
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* CE Control Register |
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*/ |
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#define CE_CONTROL_REG 0x4 |
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/* |
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* CEx Control Register |
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*/ |
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#define CONTROL_AAF_MODE BIT(31) |
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#define CONTROL_IO_MODE_MASK GENMASK(30, 28) |
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#define CONTROL_IO_DUAL_DATA BIT(29) |
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#define CONTROL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) |
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#define CONTROL_IO_QUAD_DATA BIT(30) |
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#define CONTROL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) |
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#define CONTROL_CE_INACTIVE_SHIFT 24 |
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#define CONTROL_CE_INACTIVE_MASK GENMASK(27, \ |
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CONTROL_CE_INACTIVE_SHIFT) |
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/* 0 = 16T ... 15 = 1T T=HCLK */ |
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#define CONTROL_COMMAND_SHIFT 16 |
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#define CONTROL_DUMMY_COMMAND_OUT BIT(15) |
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#define CONTROL_IO_DUMMY_HI BIT(14) |
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#define CONTROL_IO_DUMMY_HI_SHIFT 14 |
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#define CONTROL_CLK_DIV4 BIT(13) /* others */ |
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#define CONTROL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */ |
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#define CONTROL_RW_MERGE BIT(12) |
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#define CONTROL_IO_DUMMY_LO_SHIFT 6 |
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#define CONTROL_IO_DUMMY_LO GENMASK(7, \ |
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CONTROL_IO_DUMMY_LO_SHIFT) |
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#define CONTROL_IO_DUMMY_MASK (CONTROL_IO_DUMMY_HI | \ |
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CONTROL_IO_DUMMY_LO) |
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#define CONTROL_IO_DUMMY_SET(dummy) \ |
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(((((dummy) >> 2) & 0x1) << CONTROL_IO_DUMMY_HI_SHIFT) | \ |
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(((dummy) & 0x3) << CONTROL_IO_DUMMY_LO_SHIFT)) |
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#define CONTROL_CLOCK_FREQ_SEL_SHIFT 8 |
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#define CONTROL_CLOCK_FREQ_SEL_MASK GENMASK(11, \ |
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CONTROL_CLOCK_FREQ_SEL_SHIFT) |
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#define CONTROL_LSB_FIRST BIT(5) |
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#define CONTROL_CLOCK_MODE_3 BIT(4) |
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#define CONTROL_IN_DUAL_DATA BIT(3) |
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#define CONTROL_CE_STOP_ACTIVE_CONTROL BIT(2) |
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#define CONTROL_COMMAND_MODE_MASK GENMASK(1, 0) |
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#define CONTROL_COMMAND_MODE_NORMAL 0 |
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#define CONTROL_COMMAND_MODE_FREAD 1 |
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#define CONTROL_COMMAND_MODE_WRITE 2 |
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#define CONTROL_COMMAND_MODE_USER 3 |
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#define CONTROL_KEEP_MASK \ |
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(CONTROL_AAF_MODE | CONTROL_CE_INACTIVE_MASK | CONTROL_CLK_DIV4 | \ |
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CONTROL_CLOCK_FREQ_SEL_MASK | CONTROL_LSB_FIRST | CONTROL_CLOCK_MODE_3) |
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/* |
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* The Segment Register uses a 8MB unit to encode the start address |
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* and the end address of the mapping window of a flash SPI slave : |
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* |
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* | byte 1 | byte 2 | byte 3 | byte 4 | |
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* +--------+--------+--------+--------+ |
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* | end | start | 0 | 0 | |
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*/ |
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#define SEGMENT_ADDR_REG0 0x30 |
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#define SEGMENT_ADDR_START(_r) ((((_r) >> 16) & 0xFF) << 23) |
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#define SEGMENT_ADDR_END(_r) ((((_r) >> 24) & 0xFF) << 23) |
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#define SEGMENT_ADDR_VALUE(start, end) \ |
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(((((start) >> 23) & 0xFF) << 16) | ((((end) >> 23) & 0xFF) << 24)) |
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#define SEGMENT_ADDR_REG(controller, cs) \ |
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((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4) |
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/* |
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* In user mode all data bytes read or written to the chip decode address |
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* range are transferred to or from the SPI bus. The range is treated as a |
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* fifo of arbitratry 1, 2, or 4 byte width but each write has to be aligned |
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* to its size. The address within the multiple 8kB range is ignored when |
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* sending bytes to the SPI bus. |
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* |
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* On the arm architecture, as of Linux version 4.3, memcpy_fromio and |
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* memcpy_toio on little endian targets use the optimized memcpy routines |
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* that were designed for well behavied memory storage. These routines |
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* have a stutter if the source and destination are not both word aligned, |
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* once with a duplicate access to the source after aligning to the |
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* destination to a word boundary, and again with a duplicate access to |
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* the source when the final byte count is not word aligned. |
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* |
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* When writing or reading the fifo this stutter discards data or sends |
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* too much data to the fifo and can not be used by this driver. |
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* |
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* While the low level io string routines that implement the insl family do |
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* the desired accesses and memory increments, the cross architecture io |
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* macros make them essentially impossible to use on a memory mapped address |
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* instead of a a token from the call to iomap of an io port. |
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* |
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* These fifo routines use readl and friends to a constant io port and update |
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* the memory buffer pointer and count via explicit code. The final updates |
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* to len are optimistically suppressed. |
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*/ |
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static int aspeed_smc_read_from_ahb(void *buf, void __iomem *src, size_t len) |
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{ |
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size_t offset = 0; |
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if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) && |
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IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { |
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ioread32_rep(src, buf, len >> 2); |
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offset = len & ~0x3; |
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len -= offset; |
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} |
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ioread8_rep(src, (u8 *)buf + offset, len); |
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return 0; |
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} |
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static int aspeed_smc_write_to_ahb(void __iomem *dst, const void *buf, |
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size_t len) |
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{ |
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size_t offset = 0; |
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if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) && |
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IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { |
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iowrite32_rep(dst, buf, len >> 2); |
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offset = len & ~0x3; |
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len -= offset; |
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} |
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iowrite8_rep(dst, (const u8 *)buf + offset, len); |
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return 0; |
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} |
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static inline u32 aspeed_smc_chip_write_bit(struct aspeed_smc_chip *chip) |
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{ |
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return BIT(chip->controller->info->we0 + chip->cs); |
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} |
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static void aspeed_smc_chip_check_config(struct aspeed_smc_chip *chip) |
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{ |
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struct aspeed_smc_controller *controller = chip->controller; |
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u32 reg; |
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reg = readl(controller->regs + CONFIG_REG); |
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if (reg & aspeed_smc_chip_write_bit(chip)) |
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return; |
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dev_dbg(controller->dev, "config write is not set ! @%p: 0x%08x\n", |
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controller->regs + CONFIG_REG, reg); |
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reg |= aspeed_smc_chip_write_bit(chip); |
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writel(reg, controller->regs + CONFIG_REG); |
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} |
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static void aspeed_smc_start_user(struct spi_nor *nor) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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u32 ctl = chip->ctl_val[smc_base]; |
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/* |
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* When the chip is controlled in user mode, we need write |
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* access to send the opcodes to it. So check the config. |
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*/ |
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aspeed_smc_chip_check_config(chip); |
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ctl |= CONTROL_COMMAND_MODE_USER | |
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CONTROL_CE_STOP_ACTIVE_CONTROL; |
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writel(ctl, chip->ctl); |
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ctl &= ~CONTROL_CE_STOP_ACTIVE_CONTROL; |
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writel(ctl, chip->ctl); |
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} |
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static void aspeed_smc_stop_user(struct spi_nor *nor) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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u32 ctl = chip->ctl_val[smc_read]; |
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u32 ctl2 = ctl | CONTROL_COMMAND_MODE_USER | |
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CONTROL_CE_STOP_ACTIVE_CONTROL; |
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writel(ctl2, chip->ctl); /* stop user CE control */ |
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writel(ctl, chip->ctl); /* default to fread or read mode */ |
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} |
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static int aspeed_smc_prep(struct spi_nor *nor) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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mutex_lock(&chip->controller->mutex); |
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return 0; |
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} |
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static void aspeed_smc_unprep(struct spi_nor *nor) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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mutex_unlock(&chip->controller->mutex); |
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} |
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static int aspeed_smc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, |
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size_t len) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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aspeed_smc_start_user(nor); |
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aspeed_smc_write_to_ahb(chip->ahb_base, &opcode, 1); |
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aspeed_smc_read_from_ahb(buf, chip->ahb_base, len); |
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aspeed_smc_stop_user(nor); |
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return 0; |
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} |
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static int aspeed_smc_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf, |
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size_t len) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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aspeed_smc_start_user(nor); |
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aspeed_smc_write_to_ahb(chip->ahb_base, &opcode, 1); |
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aspeed_smc_write_to_ahb(chip->ahb_base, buf, len); |
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aspeed_smc_stop_user(nor); |
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return 0; |
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} |
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static void aspeed_smc_send_cmd_addr(struct spi_nor *nor, u8 cmd, u32 addr) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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__be32 temp; |
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u32 cmdaddr; |
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switch (nor->addr_width) { |
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default: |
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WARN_ONCE(1, "Unexpected address width %u, defaulting to 3\n", |
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nor->addr_width); |
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fallthrough; |
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case 3: |
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cmdaddr = addr & 0xFFFFFF; |
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cmdaddr |= cmd << 24; |
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temp = cpu_to_be32(cmdaddr); |
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aspeed_smc_write_to_ahb(chip->ahb_base, &temp, 4); |
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break; |
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case 4: |
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temp = cpu_to_be32(addr); |
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aspeed_smc_write_to_ahb(chip->ahb_base, &cmd, 1); |
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aspeed_smc_write_to_ahb(chip->ahb_base, &temp, 4); |
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break; |
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} |
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} |
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static ssize_t aspeed_smc_read_user(struct spi_nor *nor, loff_t from, |
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size_t len, u_char *read_buf) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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int i; |
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u8 dummy = 0xFF; |
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aspeed_smc_start_user(nor); |
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aspeed_smc_send_cmd_addr(nor, nor->read_opcode, from); |
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for (i = 0; i < chip->nor.read_dummy / 8; i++) |
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aspeed_smc_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy)); |
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aspeed_smc_read_from_ahb(read_buf, chip->ahb_base, len); |
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aspeed_smc_stop_user(nor); |
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return len; |
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} |
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static ssize_t aspeed_smc_write_user(struct spi_nor *nor, loff_t to, |
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size_t len, const u_char *write_buf) |
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{ |
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struct aspeed_smc_chip *chip = nor->priv; |
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aspeed_smc_start_user(nor); |
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aspeed_smc_send_cmd_addr(nor, nor->program_opcode, to); |
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aspeed_smc_write_to_ahb(chip->ahb_base, write_buf, len); |
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aspeed_smc_stop_user(nor); |
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return len; |
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} |
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static int aspeed_smc_unregister(struct aspeed_smc_controller *controller) |
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{ |
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struct aspeed_smc_chip *chip; |
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int n; |
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for (n = 0; n < controller->info->nce; n++) { |
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chip = controller->chips[n]; |
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if (chip) |
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mtd_device_unregister(&chip->nor.mtd); |
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} |
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return 0; |
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} |
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static int aspeed_smc_remove(struct platform_device *dev) |
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{ |
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return aspeed_smc_unregister(platform_get_drvdata(dev)); |
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} |
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static const struct of_device_id aspeed_smc_matches[] = { |
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{ .compatible = "aspeed,ast2400-fmc", .data = &fmc_2400_info }, |
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{ .compatible = "aspeed,ast2400-spi", .data = &spi_2400_info }, |
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{ .compatible = "aspeed,ast2500-fmc", .data = &fmc_2500_info }, |
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{ .compatible = "aspeed,ast2500-spi", .data = &spi_2500_info }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, aspeed_smc_matches); |
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|
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/* |
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* Each chip has a mapping window defined by a segment address |
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* register defining a start and an end address on the AHB bus. These |
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* addresses can be configured to fit the chip size and offer a |
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* contiguous memory region across chips. For the moment, we only |
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* check that each chip segment is valid. |
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*/ |
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static void __iomem *aspeed_smc_chip_base(struct aspeed_smc_chip *chip, |
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struct resource *res) |
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{ |
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struct aspeed_smc_controller *controller = chip->controller; |
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u32 offset = 0; |
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u32 reg; |
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if (controller->info->nce > 1) { |
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reg = readl(SEGMENT_ADDR_REG(controller, chip->cs)); |
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if (SEGMENT_ADDR_START(reg) >= SEGMENT_ADDR_END(reg)) |
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return NULL; |
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offset = SEGMENT_ADDR_START(reg) - res->start; |
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} |
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return controller->ahb_base + offset; |
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} |
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static u32 aspeed_smc_ahb_base_phy(struct aspeed_smc_controller *controller) |
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{ |
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u32 seg0_val = readl(SEGMENT_ADDR_REG(controller, 0)); |
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return SEGMENT_ADDR_START(seg0_val); |
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} |
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static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, |
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u32 size) |
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{ |
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struct aspeed_smc_controller *controller = chip->controller; |
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void __iomem *seg_reg; |
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u32 seg_oldval, seg_newval, ahb_base_phy, end; |
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ahb_base_phy = aspeed_smc_ahb_base_phy(controller); |
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seg_reg = SEGMENT_ADDR_REG(controller, cs); |
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seg_oldval = readl(seg_reg); |
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|
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/* |
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* If the chip size is not specified, use the default segment |
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* size, but take into account the possible overlap with the |
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* previous segment |
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*/ |
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if (!size) |
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size = SEGMENT_ADDR_END(seg_oldval) - start; |
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/* |
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* The segment cannot exceed the maximum window size of the |
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* controller. |
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*/ |
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if (start + size > ahb_base_phy + controller->ahb_window_size) { |
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size = ahb_base_phy + controller->ahb_window_size - start; |
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dev_warn(chip->nor.dev, "CE%d window resized to %dMB", |
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cs, size >> 20); |
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} |
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end = start + size; |
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seg_newval = SEGMENT_ADDR_VALUE(start, end); |
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writel(seg_newval, seg_reg); |
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|
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/* |
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* Restore default value if something goes wrong. The chip |
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* might have set some bogus value and we would loose access |
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* to the chip. |
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*/ |
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if (seg_newval != readl(seg_reg)) { |
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dev_err(chip->nor.dev, "CE%d window invalid", cs); |
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writel(seg_oldval, seg_reg); |
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start = SEGMENT_ADDR_START(seg_oldval); |
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end = SEGMENT_ADDR_END(seg_oldval); |
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size = end - start; |
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} |
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dev_info(chip->nor.dev, "CE%d window [ 0x%.8x - 0x%.8x ] %dMB", |
|
cs, start, end, size >> 20); |
|
|
|
return size; |
|
} |
|
|
|
/* |
|
* The segment register defines the mapping window on the AHB bus and |
|
* it needs to be configured depending on the chip size. The segment |
|
* register of the following CE also needs to be tuned in order to |
|
* provide a contiguous window across multiple chips. |
|
* |
|
* This is expected to be called in increasing CE order |
|
*/ |
|
static u32 aspeed_smc_chip_set_segment(struct aspeed_smc_chip *chip) |
|
{ |
|
struct aspeed_smc_controller *controller = chip->controller; |
|
u32 ahb_base_phy, start; |
|
u32 size = chip->nor.mtd.size; |
|
|
|
/* |
|
* Each controller has a chip size limit for direct memory |
|
* access |
|
*/ |
|
if (size > controller->info->maxsize) |
|
size = controller->info->maxsize; |
|
|
|
/* |
|
* The AST2400 SPI controller only handles one chip and does |
|
* not have segment registers. Let's use the chip size for the |
|
* AHB window. |
|
*/ |
|
if (controller->info == &spi_2400_info) |
|
goto out; |
|
|
|
/* |
|
* The AST2500 SPI controller has a HW bug when the CE0 chip |
|
* size reaches 128MB. Enforce a size limit of 120MB to |
|
* prevent the controller from using bogus settings in the |
|
* segment register. |
|
*/ |
|
if (chip->cs == 0 && controller->info == &spi_2500_info && |
|
size == SZ_128M) { |
|
size = 120 << 20; |
|
dev_info(chip->nor.dev, |
|
"CE%d window resized to %dMB (AST2500 HW quirk)", |
|
chip->cs, size >> 20); |
|
} |
|
|
|
ahb_base_phy = aspeed_smc_ahb_base_phy(controller); |
|
|
|
/* |
|
* As a start address for the current segment, use the default |
|
* start address if we are handling CE0 or use the previous |
|
* segment ending address |
|
*/ |
|
if (chip->cs) { |
|
u32 prev = readl(SEGMENT_ADDR_REG(controller, chip->cs - 1)); |
|
|
|
start = SEGMENT_ADDR_END(prev); |
|
} else { |
|
start = ahb_base_phy; |
|
} |
|
|
|
size = chip_set_segment(chip, chip->cs, start, size); |
|
|
|
/* Update chip base address on the AHB bus */ |
|
chip->ahb_base = controller->ahb_base + (start - ahb_base_phy); |
|
|
|
/* |
|
* Now, make sure the next segment does not overlap with the |
|
* current one we just configured, even if there is no |
|
* available chip. That could break access in Command Mode. |
|
*/ |
|
if (chip->cs < controller->info->nce - 1) |
|
chip_set_segment(chip, chip->cs + 1, start + size, 0); |
|
|
|
out: |
|
if (size < chip->nor.mtd.size) |
|
dev_warn(chip->nor.dev, |
|
"CE%d window too small for chip %dMB", |
|
chip->cs, (u32)chip->nor.mtd.size >> 20); |
|
|
|
return size; |
|
} |
|
|
|
static void aspeed_smc_chip_enable_write(struct aspeed_smc_chip *chip) |
|
{ |
|
struct aspeed_smc_controller *controller = chip->controller; |
|
u32 reg; |
|
|
|
reg = readl(controller->regs + CONFIG_REG); |
|
|
|
reg |= aspeed_smc_chip_write_bit(chip); |
|
writel(reg, controller->regs + CONFIG_REG); |
|
} |
|
|
|
static void aspeed_smc_chip_set_type(struct aspeed_smc_chip *chip, int type) |
|
{ |
|
struct aspeed_smc_controller *controller = chip->controller; |
|
u32 reg; |
|
|
|
chip->type = type; |
|
|
|
reg = readl(controller->regs + CONFIG_REG); |
|
reg &= ~(3 << (chip->cs * 2)); |
|
reg |= chip->type << (chip->cs * 2); |
|
writel(reg, controller->regs + CONFIG_REG); |
|
} |
|
|
|
/* |
|
* The first chip of the AST2500 FMC flash controller is strapped by |
|
* hardware, or autodetected, but other chips need to be set. Enforce |
|
* the 4B setting for all chips. |
|
*/ |
|
static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip) |
|
{ |
|
struct aspeed_smc_controller *controller = chip->controller; |
|
u32 reg; |
|
|
|
reg = readl(controller->regs + CE_CONTROL_REG); |
|
reg |= 1 << chip->cs; |
|
writel(reg, controller->regs + CE_CONTROL_REG); |
|
} |
|
|
|
/* |
|
* The AST2400 SPI flash controller does not have a CE Control |
|
* register. It uses the CE0 control register to set 4Byte mode at the |
|
* controller level. |
|
*/ |
|
static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip) |
|
{ |
|
chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B; |
|
chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B; |
|
} |
|
|
|
static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip, |
|
struct resource *res) |
|
{ |
|
struct aspeed_smc_controller *controller = chip->controller; |
|
const struct aspeed_smc_info *info = controller->info; |
|
u32 reg, base_reg; |
|
|
|
/* |
|
* Always turn on the write enable bit to allow opcodes to be |
|
* sent in user mode. |
|
*/ |
|
aspeed_smc_chip_enable_write(chip); |
|
|
|
/* The driver only supports SPI type flash */ |
|
if (info->hastype) |
|
aspeed_smc_chip_set_type(chip, smc_type_spi); |
|
|
|
/* |
|
* Configure chip base address in memory |
|
*/ |
|
chip->ahb_base = aspeed_smc_chip_base(chip, res); |
|
if (!chip->ahb_base) { |
|
dev_warn(chip->nor.dev, "CE%d window closed", chip->cs); |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* Get value of the inherited control register. U-Boot usually |
|
* does some timing calibration on the FMC chip, so it's good |
|
* to keep them. In the future, we should handle calibration |
|
* from Linux. |
|
*/ |
|
reg = readl(chip->ctl); |
|
dev_dbg(controller->dev, "control register: %08x\n", reg); |
|
|
|
base_reg = reg & CONTROL_KEEP_MASK; |
|
if (base_reg != reg) { |
|
dev_dbg(controller->dev, |
|
"control register changed to: %08x\n", |
|
base_reg); |
|
} |
|
chip->ctl_val[smc_base] = base_reg; |
|
|
|
/* |
|
* Retain the prior value of the control register as the |
|
* default if it was normal access mode. Otherwise start with |
|
* the sanitized base value set to read mode. |
|
*/ |
|
if ((reg & CONTROL_COMMAND_MODE_MASK) == |
|
CONTROL_COMMAND_MODE_NORMAL) |
|
chip->ctl_val[smc_read] = reg; |
|
else |
|
chip->ctl_val[smc_read] = chip->ctl_val[smc_base] | |
|
CONTROL_COMMAND_MODE_NORMAL; |
|
|
|
dev_dbg(controller->dev, "default control register: %08x\n", |
|
chip->ctl_val[smc_read]); |
|
return 0; |
|
} |
|
|
|
static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip) |
|
{ |
|
struct aspeed_smc_controller *controller = chip->controller; |
|
const struct aspeed_smc_info *info = controller->info; |
|
u32 cmd; |
|
|
|
if (chip->nor.addr_width == 4 && info->set_4b) |
|
info->set_4b(chip); |
|
|
|
/* This is for direct AHB access when using Command Mode. */ |
|
chip->ahb_window_size = aspeed_smc_chip_set_segment(chip); |
|
|
|
/* |
|
* base mode has not been optimized yet. use it for writes. |
|
*/ |
|
chip->ctl_val[smc_write] = chip->ctl_val[smc_base] | |
|
chip->nor.program_opcode << CONTROL_COMMAND_SHIFT | |
|
CONTROL_COMMAND_MODE_WRITE; |
|
|
|
dev_dbg(controller->dev, "write control register: %08x\n", |
|
chip->ctl_val[smc_write]); |
|
|
|
/* |
|
* TODO: Adjust clocks if fast read is supported and interpret |
|
* SPI NOR flags to adjust controller settings. |
|
*/ |
|
if (chip->nor.read_proto == SNOR_PROTO_1_1_1) { |
|
if (chip->nor.read_dummy == 0) |
|
cmd = CONTROL_COMMAND_MODE_NORMAL; |
|
else |
|
cmd = CONTROL_COMMAND_MODE_FREAD; |
|
} else { |
|
dev_err(chip->nor.dev, "unsupported SPI read mode\n"); |
|
return -EINVAL; |
|
} |
|
|
|
chip->ctl_val[smc_read] |= cmd | |
|
CONTROL_IO_DUMMY_SET(chip->nor.read_dummy / 8); |
|
|
|
dev_dbg(controller->dev, "base control register: %08x\n", |
|
chip->ctl_val[smc_read]); |
|
return 0; |
|
} |
|
|
|
static const struct spi_nor_controller_ops aspeed_smc_controller_ops = { |
|
.prepare = aspeed_smc_prep, |
|
.unprepare = aspeed_smc_unprep, |
|
.read_reg = aspeed_smc_read_reg, |
|
.write_reg = aspeed_smc_write_reg, |
|
.read = aspeed_smc_read_user, |
|
.write = aspeed_smc_write_user, |
|
}; |
|
|
|
static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller, |
|
struct device_node *np, struct resource *r) |
|
{ |
|
const struct spi_nor_hwcaps hwcaps = { |
|
.mask = SNOR_HWCAPS_READ | |
|
SNOR_HWCAPS_READ_FAST | |
|
SNOR_HWCAPS_PP, |
|
}; |
|
const struct aspeed_smc_info *info = controller->info; |
|
struct device *dev = controller->dev; |
|
struct device_node *child; |
|
unsigned int cs; |
|
int ret = -ENODEV; |
|
|
|
for_each_available_child_of_node(np, child) { |
|
struct aspeed_smc_chip *chip; |
|
struct spi_nor *nor; |
|
struct mtd_info *mtd; |
|
|
|
/* This driver does not support NAND or NOR flash devices. */ |
|
if (!of_device_is_compatible(child, "jedec,spi-nor")) |
|
continue; |
|
|
|
ret = of_property_read_u32(child, "reg", &cs); |
|
if (ret) { |
|
dev_err(dev, "Couldn't not read chip select.\n"); |
|
break; |
|
} |
|
|
|
if (cs >= info->nce) { |
|
dev_err(dev, "Chip select %d out of range.\n", |
|
cs); |
|
ret = -ERANGE; |
|
break; |
|
} |
|
|
|
if (controller->chips[cs]) { |
|
dev_err(dev, "Chip select %d already in use by %s\n", |
|
cs, dev_name(controller->chips[cs]->nor.dev)); |
|
ret = -EBUSY; |
|
break; |
|
} |
|
|
|
chip = devm_kzalloc(controller->dev, sizeof(*chip), GFP_KERNEL); |
|
if (!chip) { |
|
ret = -ENOMEM; |
|
break; |
|
} |
|
|
|
chip->controller = controller; |
|
chip->ctl = controller->regs + info->ctl0 + cs * 4; |
|
chip->cs = cs; |
|
|
|
nor = &chip->nor; |
|
mtd = &nor->mtd; |
|
|
|
nor->dev = dev; |
|
nor->priv = chip; |
|
spi_nor_set_flash_node(nor, child); |
|
nor->controller_ops = &aspeed_smc_controller_ops; |
|
|
|
ret = aspeed_smc_chip_setup_init(chip, r); |
|
if (ret) |
|
break; |
|
|
|
/* |
|
* TODO: Add support for Dual and Quad SPI protocols |
|
* attach when board support is present as determined |
|
* by of property. |
|
*/ |
|
ret = spi_nor_scan(nor, NULL, &hwcaps); |
|
if (ret) |
|
break; |
|
|
|
ret = aspeed_smc_chip_setup_finish(chip); |
|
if (ret) |
|
break; |
|
|
|
ret = mtd_device_register(mtd, NULL, 0); |
|
if (ret) |
|
break; |
|
|
|
controller->chips[cs] = chip; |
|
} |
|
|
|
if (ret) { |
|
of_node_put(child); |
|
aspeed_smc_unregister(controller); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int aspeed_smc_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
struct device *dev = &pdev->dev; |
|
struct aspeed_smc_controller *controller; |
|
const struct of_device_id *match; |
|
const struct aspeed_smc_info *info; |
|
struct resource *res; |
|
int ret; |
|
|
|
match = of_match_device(aspeed_smc_matches, &pdev->dev); |
|
if (!match || !match->data) |
|
return -ENODEV; |
|
info = match->data; |
|
|
|
controller = devm_kzalloc(&pdev->dev, |
|
struct_size(controller, chips, info->nce), |
|
GFP_KERNEL); |
|
if (!controller) |
|
return -ENOMEM; |
|
controller->info = info; |
|
controller->dev = dev; |
|
|
|
mutex_init(&controller->mutex); |
|
platform_set_drvdata(pdev, controller); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
controller->regs = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(controller->regs)) |
|
return PTR_ERR(controller->regs); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
|
controller->ahb_base = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(controller->ahb_base)) |
|
return PTR_ERR(controller->ahb_base); |
|
|
|
controller->ahb_window_size = resource_size(res); |
|
|
|
ret = aspeed_smc_setup_flash(controller, np, res); |
|
if (ret) |
|
dev_err(dev, "Aspeed SMC probe failed %d\n", ret); |
|
|
|
return ret; |
|
} |
|
|
|
static struct platform_driver aspeed_smc_driver = { |
|
.probe = aspeed_smc_probe, |
|
.remove = aspeed_smc_remove, |
|
.driver = { |
|
.name = DEVICE_NAME, |
|
.of_match_table = aspeed_smc_matches, |
|
} |
|
}; |
|
|
|
module_platform_driver(aspeed_smc_driver); |
|
|
|
MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver"); |
|
MODULE_AUTHOR("Cedric Le Goater <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|