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617 lines
15 KiB
617 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* OneNAND driver for OMAP2 / OMAP3 |
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* |
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* Copyright © 2005-2006 Nokia Corporation |
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* |
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* Author: Jarkko Lavinen <[email protected]> and Juha Yrjölä |
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* IRQ and DMA support written by Timo Teras |
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*/ |
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|
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#include <linux/device.h> |
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#include <linux/module.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/onenand.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/of_device.h> |
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#include <linux/omap-gpmc.h> |
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#include <linux/platform_device.h> |
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#include <linux/interrupt.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/dmaengine.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/gpio/consumer.h> |
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#include <asm/mach/flash.h> |
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#define DRIVER_NAME "omap2-onenand" |
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#define ONENAND_BUFRAM_SIZE (1024 * 5) |
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struct omap2_onenand { |
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struct platform_device *pdev; |
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int gpmc_cs; |
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unsigned long phys_base; |
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struct gpio_desc *int_gpiod; |
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struct mtd_info mtd; |
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struct onenand_chip onenand; |
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struct completion irq_done; |
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struct completion dma_done; |
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struct dma_chan *dma_chan; |
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}; |
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static void omap2_onenand_dma_complete_func(void *completion) |
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{ |
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complete(completion); |
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} |
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static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id) |
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{ |
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struct omap2_onenand *c = dev_id; |
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complete(&c->irq_done); |
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return IRQ_HANDLED; |
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} |
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static inline unsigned short read_reg(struct omap2_onenand *c, int reg) |
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{ |
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return readw(c->onenand.base + reg); |
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} |
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static inline void write_reg(struct omap2_onenand *c, unsigned short value, |
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int reg) |
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{ |
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writew(value, c->onenand.base + reg); |
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} |
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static int omap2_onenand_set_cfg(struct omap2_onenand *c, |
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bool sr, bool sw, |
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int latency, int burst_len) |
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{ |
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unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT; |
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reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT; |
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switch (burst_len) { |
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case 0: /* continuous */ |
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break; |
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case 4: |
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reg |= ONENAND_SYS_CFG1_BL_4; |
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break; |
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case 8: |
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reg |= ONENAND_SYS_CFG1_BL_8; |
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break; |
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case 16: |
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reg |= ONENAND_SYS_CFG1_BL_16; |
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break; |
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case 32: |
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reg |= ONENAND_SYS_CFG1_BL_32; |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (latency > 5) |
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reg |= ONENAND_SYS_CFG1_HF; |
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if (latency > 7) |
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reg |= ONENAND_SYS_CFG1_VHF; |
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if (sr) |
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reg |= ONENAND_SYS_CFG1_SYNC_READ; |
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if (sw) |
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reg |= ONENAND_SYS_CFG1_SYNC_WRITE; |
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write_reg(c, reg, ONENAND_REG_SYS_CFG1); |
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return 0; |
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} |
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static int omap2_onenand_get_freq(int ver) |
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{ |
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switch ((ver >> 4) & 0xf) { |
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case 0: |
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return 40; |
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case 1: |
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return 54; |
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case 2: |
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return 66; |
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case 3: |
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return 83; |
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case 4: |
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return 104; |
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} |
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return -EINVAL; |
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} |
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static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr) |
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{ |
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printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n", |
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msg, state, ctrl, intr); |
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} |
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static void wait_warn(char *msg, int state, unsigned int ctrl, |
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unsigned int intr) |
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{ |
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printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x " |
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"intr 0x%04x\n", msg, state, ctrl, intr); |
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} |
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static int omap2_onenand_wait(struct mtd_info *mtd, int state) |
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{ |
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struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd); |
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struct onenand_chip *this = mtd->priv; |
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unsigned int intr = 0; |
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unsigned int ctrl, ctrl_mask; |
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unsigned long timeout; |
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u32 syscfg; |
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if (state == FL_RESETTING || state == FL_PREPARING_ERASE || |
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state == FL_VERIFYING_ERASE) { |
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int i = 21; |
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unsigned int intr_flags = ONENAND_INT_MASTER; |
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switch (state) { |
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case FL_RESETTING: |
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intr_flags |= ONENAND_INT_RESET; |
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break; |
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case FL_PREPARING_ERASE: |
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intr_flags |= ONENAND_INT_ERASE; |
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break; |
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case FL_VERIFYING_ERASE: |
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i = 101; |
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break; |
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} |
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while (--i) { |
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udelay(1); |
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intr = read_reg(c, ONENAND_REG_INTERRUPT); |
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if (intr & ONENAND_INT_MASTER) |
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break; |
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} |
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); |
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if (ctrl & ONENAND_CTRL_ERROR) { |
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wait_err("controller error", state, ctrl, intr); |
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return -EIO; |
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} |
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if ((intr & intr_flags) == intr_flags) |
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return 0; |
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/* Continue in wait for interrupt branch */ |
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} |
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if (state != FL_READING) { |
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int result; |
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/* Turn interrupts on */ |
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syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); |
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if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) { |
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syscfg |= ONENAND_SYS_CFG1_IOBE; |
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write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); |
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/* Add a delay to let GPIO settle */ |
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syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); |
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} |
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reinit_completion(&c->irq_done); |
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result = gpiod_get_value(c->int_gpiod); |
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if (result < 0) { |
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); |
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intr = read_reg(c, ONENAND_REG_INTERRUPT); |
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wait_err("gpio error", state, ctrl, intr); |
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return result; |
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} else if (result == 0) { |
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int retry_cnt = 0; |
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retry: |
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if (!wait_for_completion_io_timeout(&c->irq_done, |
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msecs_to_jiffies(20))) { |
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/* Timeout after 20ms */ |
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); |
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if (ctrl & ONENAND_CTRL_ONGO && |
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!this->ongoing) { |
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/* |
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* The operation seems to be still going |
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* so give it some more time. |
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*/ |
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retry_cnt += 1; |
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if (retry_cnt < 3) |
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goto retry; |
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intr = read_reg(c, |
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ONENAND_REG_INTERRUPT); |
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wait_err("timeout", state, ctrl, intr); |
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return -EIO; |
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} |
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intr = read_reg(c, ONENAND_REG_INTERRUPT); |
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if ((intr & ONENAND_INT_MASTER) == 0) |
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wait_warn("timeout", state, ctrl, intr); |
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} |
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} |
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} else { |
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int retry_cnt = 0; |
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/* Turn interrupts off */ |
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syscfg = read_reg(c, ONENAND_REG_SYS_CFG1); |
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syscfg &= ~ONENAND_SYS_CFG1_IOBE; |
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write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); |
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timeout = jiffies + msecs_to_jiffies(20); |
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while (1) { |
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if (time_before(jiffies, timeout)) { |
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intr = read_reg(c, ONENAND_REG_INTERRUPT); |
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if (intr & ONENAND_INT_MASTER) |
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break; |
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} else { |
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/* Timeout after 20ms */ |
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); |
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if (ctrl & ONENAND_CTRL_ONGO) { |
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/* |
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* The operation seems to be still going |
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* so give it some more time. |
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*/ |
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retry_cnt += 1; |
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if (retry_cnt < 3) { |
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timeout = jiffies + |
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msecs_to_jiffies(20); |
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continue; |
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} |
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} |
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break; |
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} |
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} |
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} |
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intr = read_reg(c, ONENAND_REG_INTERRUPT); |
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ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); |
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if (intr & ONENAND_INT_READ) { |
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int ecc = read_reg(c, ONENAND_REG_ECC_STATUS); |
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if (ecc) { |
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unsigned int addr1, addr8; |
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addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1); |
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addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8); |
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if (ecc & ONENAND_ECC_2BIT_ALL) { |
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printk(KERN_ERR "onenand_wait: ECC error = " |
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"0x%04x, addr1 %#x, addr8 %#x\n", |
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ecc, addr1, addr8); |
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mtd->ecc_stats.failed++; |
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return -EBADMSG; |
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} else if (ecc & ONENAND_ECC_1BIT_ALL) { |
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printk(KERN_NOTICE "onenand_wait: correctable " |
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"ECC error = 0x%04x, addr1 %#x, " |
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"addr8 %#x\n", ecc, addr1, addr8); |
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mtd->ecc_stats.corrected++; |
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} |
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} |
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} else if (state == FL_READING) { |
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wait_err("timeout", state, ctrl, intr); |
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return -EIO; |
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} |
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if (ctrl & ONENAND_CTRL_ERROR) { |
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wait_err("controller error", state, ctrl, intr); |
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if (ctrl & ONENAND_CTRL_LOCK) |
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printk(KERN_ERR "onenand_wait: " |
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"Device is write protected!!!\n"); |
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return -EIO; |
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} |
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ctrl_mask = 0xFE9F; |
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if (this->ongoing) |
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ctrl_mask &= ~0x8000; |
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if (ctrl & ctrl_mask) |
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wait_warn("unexpected controller status", state, ctrl, intr); |
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return 0; |
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} |
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static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area) |
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{ |
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struct onenand_chip *this = mtd->priv; |
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if (ONENAND_CURRENT_BUFFERRAM(this)) { |
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if (area == ONENAND_DATARAM) |
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return this->writesize; |
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if (area == ONENAND_SPARERAM) |
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return mtd->oobsize; |
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} |
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return 0; |
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} |
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static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c, |
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dma_addr_t src, dma_addr_t dst, |
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size_t count) |
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{ |
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struct dma_async_tx_descriptor *tx; |
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dma_cookie_t cookie; |
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tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, |
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DMA_CTRL_ACK | DMA_PREP_INTERRUPT); |
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if (!tx) { |
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dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n"); |
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return -EIO; |
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} |
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reinit_completion(&c->dma_done); |
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tx->callback = omap2_onenand_dma_complete_func; |
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tx->callback_param = &c->dma_done; |
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cookie = tx->tx_submit(tx); |
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if (dma_submit_error(cookie)) { |
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dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n"); |
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return -EIO; |
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} |
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dma_async_issue_pending(c->dma_chan); |
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if (!wait_for_completion_io_timeout(&c->dma_done, |
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msecs_to_jiffies(20))) { |
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dmaengine_terminate_sync(c->dma_chan); |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area, |
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unsigned char *buffer, int offset, |
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size_t count) |
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{ |
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struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd); |
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struct onenand_chip *this = mtd->priv; |
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struct device *dev = &c->pdev->dev; |
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void *buf = (void *)buffer; |
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dma_addr_t dma_src, dma_dst; |
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int bram_offset, err; |
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size_t xtra; |
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bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset; |
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/* |
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* If the buffer address is not DMA-able, len is not long enough to |
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* make DMA transfers profitable or if invoked from panic_write() |
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* fallback to PIO mode. |
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*/ |
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if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 || |
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count < 384 || mtd->oops_panic_write) |
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goto out_copy; |
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xtra = count & 3; |
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if (xtra) { |
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count -= xtra; |
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memcpy(buf + count, this->base + bram_offset + count, xtra); |
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} |
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dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE); |
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dma_src = c->phys_base + bram_offset; |
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if (dma_mapping_error(dev, dma_dst)) { |
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dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count); |
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goto out_copy; |
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} |
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err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count); |
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dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE); |
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if (!err) |
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return 0; |
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dev_err(dev, "timeout waiting for DMA\n"); |
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out_copy: |
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memcpy(buf, this->base + bram_offset, count); |
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return 0; |
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} |
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static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area, |
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const unsigned char *buffer, |
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int offset, size_t count) |
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{ |
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struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd); |
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struct onenand_chip *this = mtd->priv; |
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struct device *dev = &c->pdev->dev; |
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void *buf = (void *)buffer; |
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dma_addr_t dma_src, dma_dst; |
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int bram_offset, err; |
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bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset; |
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/* |
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* If the buffer address is not DMA-able, len is not long enough to |
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* make DMA transfers profitable or if invoked from panic_write() |
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* fallback to PIO mode. |
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*/ |
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if (!virt_addr_valid(buf) || bram_offset & 3 || (size_t)buf & 3 || |
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count < 384 || mtd->oops_panic_write) |
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goto out_copy; |
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dma_src = dma_map_single(dev, buf, count, DMA_TO_DEVICE); |
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dma_dst = c->phys_base + bram_offset; |
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if (dma_mapping_error(dev, dma_src)) { |
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dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count); |
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goto out_copy; |
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} |
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err = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count); |
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dma_unmap_page(dev, dma_src, count, DMA_TO_DEVICE); |
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if (!err) |
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return 0; |
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dev_err(dev, "timeout waiting for DMA\n"); |
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out_copy: |
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memcpy(this->base + bram_offset, buf, count); |
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return 0; |
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} |
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static void omap2_onenand_shutdown(struct platform_device *pdev) |
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{ |
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struct omap2_onenand *c = dev_get_drvdata(&pdev->dev); |
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/* With certain content in the buffer RAM, the OMAP boot ROM code |
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* can recognize the flash chip incorrectly. Zero it out before |
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* soft reset. |
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*/ |
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memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE); |
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} |
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static int omap2_onenand_probe(struct platform_device *pdev) |
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{ |
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u32 val; |
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dma_cap_mask_t mask; |
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int freq, latency, r; |
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struct resource *res; |
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struct omap2_onenand *c; |
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struct gpmc_onenand_info info; |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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dev_err(dev, "error getting memory resource\n"); |
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return -EINVAL; |
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} |
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r = of_property_read_u32(np, "reg", &val); |
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if (r) { |
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dev_err(dev, "reg not found in DT\n"); |
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return r; |
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} |
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c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL); |
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if (!c) |
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return -ENOMEM; |
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init_completion(&c->irq_done); |
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init_completion(&c->dma_done); |
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c->gpmc_cs = val; |
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c->phys_base = res->start; |
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c->onenand.base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(c->onenand.base)) |
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return PTR_ERR(c->onenand.base); |
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c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN); |
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if (IS_ERR(c->int_gpiod)) { |
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/* Just try again if this happens */ |
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return dev_err_probe(dev, PTR_ERR(c->int_gpiod), "error getting gpio\n"); |
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} |
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if (c->int_gpiod) { |
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r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod), |
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omap2_onenand_interrupt, |
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IRQF_TRIGGER_RISING, "onenand", c); |
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if (r) |
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return r; |
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c->onenand.wait = omap2_onenand_wait; |
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} |
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dma_cap_zero(mask); |
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dma_cap_set(DMA_MEMCPY, mask); |
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c->dma_chan = dma_request_channel(mask, NULL, NULL); |
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if (c->dma_chan) { |
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c->onenand.read_bufferram = omap2_onenand_read_bufferram; |
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c->onenand.write_bufferram = omap2_onenand_write_bufferram; |
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} |
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c->pdev = pdev; |
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c->mtd.priv = &c->onenand; |
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c->mtd.dev.parent = dev; |
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mtd_set_of_node(&c->mtd, dev->of_node); |
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dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n", |
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c->gpmc_cs, c->phys_base, c->onenand.base, |
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c->dma_chan ? "DMA" : "PIO"); |
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r = onenand_scan(&c->mtd, 1); |
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if (r < 0) |
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goto err_release_dma; |
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freq = omap2_onenand_get_freq(c->onenand.version_id); |
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if (freq > 0) { |
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switch (freq) { |
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case 104: |
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latency = 7; |
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break; |
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case 83: |
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latency = 6; |
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break; |
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case 66: |
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latency = 5; |
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break; |
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case 56: |
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latency = 4; |
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break; |
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default: /* 40 MHz or lower */ |
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latency = 3; |
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break; |
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} |
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r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs, |
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freq, latency, &info); |
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if (r) |
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goto err_release_onenand; |
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r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write, |
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latency, info.burst_len); |
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if (r) |
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goto err_release_onenand; |
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|
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if (info.sync_read || info.sync_write) |
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dev_info(dev, "optimized timings for %d MHz\n", freq); |
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} |
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|
|
r = mtd_device_register(&c->mtd, NULL, 0); |
|
if (r) |
|
goto err_release_onenand; |
|
|
|
platform_set_drvdata(pdev, c); |
|
|
|
return 0; |
|
|
|
err_release_onenand: |
|
onenand_release(&c->mtd); |
|
err_release_dma: |
|
if (c->dma_chan) |
|
dma_release_channel(c->dma_chan); |
|
|
|
return r; |
|
} |
|
|
|
static int omap2_onenand_remove(struct platform_device *pdev) |
|
{ |
|
struct omap2_onenand *c = dev_get_drvdata(&pdev->dev); |
|
|
|
onenand_release(&c->mtd); |
|
if (c->dma_chan) |
|
dma_release_channel(c->dma_chan); |
|
omap2_onenand_shutdown(pdev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id omap2_onenand_id_table[] = { |
|
{ .compatible = "ti,omap2-onenand", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, omap2_onenand_id_table); |
|
|
|
static struct platform_driver omap2_onenand_driver = { |
|
.probe = omap2_onenand_probe, |
|
.remove = omap2_onenand_remove, |
|
.shutdown = omap2_onenand_shutdown, |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.of_match_table = omap2_onenand_id_table, |
|
}, |
|
}; |
|
|
|
module_platform_driver(omap2_onenand_driver); |
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Jarkko Lavinen <[email protected]>"); |
|
MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");
|
|
|