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577 lines
19 KiB
577 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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#ifndef __CARD_BASE_H__ |
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#define __CARD_BASE_H__ |
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/** |
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* IBM Accelerator Family 'GenWQE' |
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* |
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* (C) Copyright IBM Corp. 2013 |
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* |
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* Author: Frank Haverkamp <[email protected]> |
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* Author: Joerg-Stephan Vogt <[email protected]> |
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* Author: Michael Jung <[email protected]> |
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* Author: Michael Ruettger <[email protected]> |
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*/ |
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/* |
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* Interfaces within the GenWQE module. Defines genwqe_card and |
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* ddcb_queue as well as ddcb_requ. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/cdev.h> |
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#include <linux/stringify.h> |
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#include <linux/pci.h> |
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#include <linux/semaphore.h> |
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#include <linux/uaccess.h> |
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#include <linux/io.h> |
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#include <linux/debugfs.h> |
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#include <linux/slab.h> |
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#include <linux/genwqe/genwqe_card.h> |
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#include "genwqe_driver.h" |
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#define GENWQE_MSI_IRQS 4 /* Just one supported, no MSIx */ |
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#define GENWQE_MAX_VFS 15 /* maximum 15 VFs are possible */ |
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#define GENWQE_MAX_FUNCS 16 /* 1 PF and 15 VFs */ |
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#define GENWQE_CARD_NO_MAX (16 * GENWQE_MAX_FUNCS) |
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/* Compile parameters, some of them appear in debugfs for later adjustment */ |
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#define GENWQE_DDCB_MAX 32 /* DDCBs on the work-queue */ |
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#define GENWQE_POLLING_ENABLED 0 /* in case of irqs not working */ |
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#define GENWQE_DDCB_SOFTWARE_TIMEOUT 10 /* timeout per DDCB in seconds */ |
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#define GENWQE_KILL_TIMEOUT 8 /* time until process gets killed */ |
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#define GENWQE_VF_JOBTIMEOUT_MSEC 250 /* 250 msec */ |
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#define GENWQE_PF_JOBTIMEOUT_MSEC 8000 /* 8 sec should be ok */ |
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#define GENWQE_HEALTH_CHECK_INTERVAL 4 /* <= 0: disabled */ |
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/* Sysfs attribute groups used when we create the genwqe device */ |
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extern const struct attribute_group *genwqe_attribute_groups[]; |
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/* |
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* Config space for Genwqe5 A7: |
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* 00:[14 10 4b 04]40 00 10 00[00 00 00 12]00 00 00 00 |
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* 10: 0c 00 00 f0 07 3c 00 00 00 00 00 00 00 00 00 00 |
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* 20: 00 00 00 00 00 00 00 00 00 00 00 00[14 10 4b 04] |
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* 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 |
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*/ |
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#define PCI_DEVICE_GENWQE 0x044b /* Genwqe DeviceID */ |
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#define PCI_SUBSYSTEM_ID_GENWQE5 0x035f /* Genwqe A5 Subsystem-ID */ |
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#define PCI_SUBSYSTEM_ID_GENWQE5_NEW 0x044b /* Genwqe A5 Subsystem-ID */ |
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#define PCI_CLASSCODE_GENWQE5 0x1200 /* UNKNOWN */ |
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#define PCI_SUBVENDOR_ID_IBM_SRIOV 0x0000 |
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#define PCI_SUBSYSTEM_ID_GENWQE5_SRIOV 0x0000 /* Genwqe A5 Subsystem-ID */ |
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#define PCI_CLASSCODE_GENWQE5_SRIOV 0x1200 /* UNKNOWN */ |
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#define GENWQE_SLU_ARCH_REQ 2 /* Required SLU architecture level */ |
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/** |
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* struct genwqe_reg - Genwqe data dump functionality |
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*/ |
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struct genwqe_reg { |
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u32 addr; |
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u32 idx; |
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u64 val; |
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}; |
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/* |
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* enum genwqe_dbg_type - Specify chip unit to dump/debug |
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*/ |
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enum genwqe_dbg_type { |
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GENWQE_DBG_UNIT0 = 0, /* captured before prev errs cleared */ |
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GENWQE_DBG_UNIT1 = 1, |
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GENWQE_DBG_UNIT2 = 2, |
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GENWQE_DBG_UNIT3 = 3, |
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GENWQE_DBG_UNIT4 = 4, |
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GENWQE_DBG_UNIT5 = 5, |
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GENWQE_DBG_UNIT6 = 6, |
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GENWQE_DBG_UNIT7 = 7, |
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GENWQE_DBG_REGS = 8, |
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GENWQE_DBG_DMA = 9, |
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GENWQE_DBG_UNITS = 10, /* max number of possible debug units */ |
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}; |
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/* Software error injection to simulate card failures */ |
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#define GENWQE_INJECT_HARDWARE_FAILURE 0x00000001 /* injects -1 reg reads */ |
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#define GENWQE_INJECT_BUS_RESET_FAILURE 0x00000002 /* pci_bus_reset fail */ |
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#define GENWQE_INJECT_GFIR_FATAL 0x00000004 /* GFIR = 0x0000ffff */ |
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#define GENWQE_INJECT_GFIR_INFO 0x00000008 /* GFIR = 0xffff0000 */ |
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/* |
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* Genwqe card description and management data. |
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* |
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* Error-handling in case of card malfunction |
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* ------------------------------------------ |
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* |
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* If the card is detected to be defective the outside environment |
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* will cause the PCI layer to call deinit (the cleanup function for |
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* probe). This is the same effect like doing a unbind/bind operation |
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* on the card. |
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* |
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* The genwqe card driver implements a health checking thread which |
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* verifies the card function. If this detects a problem the cards |
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* device is being shutdown and restarted again, along with a reset of |
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* the card and queue. |
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* |
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* All functions accessing the card device return either -EIO or -ENODEV |
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* code to indicate the malfunction to the user. The user has to close |
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* the file descriptor and open a new one, once the card becomes |
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* available again. |
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* |
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* If the open file descriptor is setup to receive SIGIO, the signal is |
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* genereated for the application which has to provide a handler to |
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* react on it. If the application does not close the open |
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* file descriptor a SIGKILL is send to enforce freeing the cards |
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* resources. |
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* |
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* I did not find a different way to prevent kernel problems due to |
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* reference counters for the cards character devices getting out of |
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* sync. The character device deallocation does not block, even if |
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* there is still an open file descriptor pending. If this pending |
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* descriptor is closed, the data structures used by the character |
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* device is reinstantiated, which will lead to the reference counter |
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* dropping below the allowed values. |
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* |
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* Card recovery |
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* ------------- |
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* |
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* To test the internal driver recovery the following command can be used: |
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* sudo sh -c 'echo 0xfffff > /sys/class/genwqe/genwqe0_card/err_inject' |
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*/ |
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/** |
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* struct dma_mapping_type - Mapping type definition |
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* |
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* To avoid memcpying data arround we use user memory directly. To do |
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* this we need to pin/swap-in the memory and request a DMA address |
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* for it. |
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*/ |
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enum dma_mapping_type { |
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GENWQE_MAPPING_RAW = 0, /* contignous memory buffer */ |
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GENWQE_MAPPING_SGL_TEMP, /* sglist dynamically used */ |
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GENWQE_MAPPING_SGL_PINNED, /* sglist used with pinning */ |
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}; |
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/** |
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* struct dma_mapping - Information about memory mappings done by the driver |
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*/ |
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struct dma_mapping { |
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enum dma_mapping_type type; |
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void *u_vaddr; /* user-space vaddr/non-aligned */ |
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void *k_vaddr; /* kernel-space vaddr/non-aligned */ |
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dma_addr_t dma_addr; /* physical DMA address */ |
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struct page **page_list; /* list of pages used by user buff */ |
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dma_addr_t *dma_list; /* list of dma addresses per page */ |
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unsigned int nr_pages; /* number of pages */ |
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unsigned int size; /* size in bytes */ |
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struct list_head card_list; /* list of usr_maps for card */ |
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struct list_head pin_list; /* list of pinned memory for dev */ |
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int write; /* writable map? useful in unmapping */ |
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}; |
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static inline void genwqe_mapping_init(struct dma_mapping *m, |
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enum dma_mapping_type type) |
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{ |
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memset(m, 0, sizeof(*m)); |
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m->type = type; |
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m->write = 1; /* Assume the maps we create are R/W */ |
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} |
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/** |
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* struct ddcb_queue - DDCB queue data |
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* @ddcb_max: Number of DDCBs on the queue |
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* @ddcb_next: Next free DDCB |
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* @ddcb_act: Next DDCB supposed to finish |
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* @ddcb_seq: Sequence number of last DDCB |
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* @ddcbs_in_flight: Currently enqueued DDCBs |
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* @ddcbs_completed: Number of already completed DDCBs |
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* @return_on_busy: Number of -EBUSY returns on full queue |
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* @wait_on_busy: Number of waits on full queue |
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* @ddcb_daddr: DMA address of first DDCB in the queue |
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* @ddcb_vaddr: Kernel virtual address of first DDCB in the queue |
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* @ddcb_req: Associated requests (one per DDCB) |
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* @ddcb_waitqs: Associated wait queues (one per DDCB) |
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* @ddcb_lock: Lock to protect queuing operations |
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* @ddcb_waitq: Wait on next DDCB finishing |
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*/ |
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struct ddcb_queue { |
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int ddcb_max; /* amount of DDCBs */ |
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int ddcb_next; /* next available DDCB num */ |
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int ddcb_act; /* DDCB to be processed */ |
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u16 ddcb_seq; /* slc seq num */ |
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unsigned int ddcbs_in_flight; /* number of ddcbs in processing */ |
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unsigned int ddcbs_completed; |
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unsigned int ddcbs_max_in_flight; |
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unsigned int return_on_busy; /* how many times -EBUSY? */ |
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unsigned int wait_on_busy; |
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dma_addr_t ddcb_daddr; /* DMA address */ |
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struct ddcb *ddcb_vaddr; /* kernel virtual addr for DDCBs */ |
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struct ddcb_requ **ddcb_req; /* ddcb processing parameter */ |
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wait_queue_head_t *ddcb_waitqs; /* waitqueue per ddcb */ |
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spinlock_t ddcb_lock; /* exclusive access to queue */ |
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wait_queue_head_t busy_waitq; /* wait for ddcb processing */ |
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/* registers or the respective queue to be used */ |
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u32 IO_QUEUE_CONFIG; |
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u32 IO_QUEUE_STATUS; |
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u32 IO_QUEUE_SEGMENT; |
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u32 IO_QUEUE_INITSQN; |
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u32 IO_QUEUE_WRAP; |
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u32 IO_QUEUE_OFFSET; |
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u32 IO_QUEUE_WTIME; |
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u32 IO_QUEUE_ERRCNTS; |
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u32 IO_QUEUE_LRW; |
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}; |
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/* |
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* GFIR, SLU_UNITCFG, APP_UNITCFG |
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* 8 Units with FIR/FEC + 64 * 2ndary FIRS/FEC. |
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*/ |
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#define GENWQE_FFDC_REGS (3 + (8 * (2 + 2 * 64))) |
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struct genwqe_ffdc { |
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unsigned int entries; |
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struct genwqe_reg *regs; |
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}; |
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/** |
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* struct genwqe_dev - GenWQE device information |
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* @card_state: Card operation state, see above |
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* @ffdc: First Failure Data Capture buffers for each unit |
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* @card_thread: Working thread to operate the DDCB queue |
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* @card_waitq: Wait queue used in card_thread |
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* @queue: DDCB queue |
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* @health_thread: Card monitoring thread (only for PFs) |
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* @health_waitq: Wait queue used in health_thread |
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* @pci_dev: Associated PCI device (function) |
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* @mmio: Base address of 64-bit register space |
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* @mmio_len: Length of register area |
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* @file_lock: Lock to protect access to file_list |
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* @file_list: List of all processes with open GenWQE file descriptors |
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* |
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* This struct contains all information needed to communicate with a |
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* GenWQE card. It is initialized when a GenWQE device is found and |
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* destroyed when it goes away. It holds data to maintain the queue as |
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* well as data needed to feed the user interfaces. |
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*/ |
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struct genwqe_dev { |
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enum genwqe_card_state card_state; |
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spinlock_t print_lock; |
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int card_idx; /* card index 0..CARD_NO_MAX-1 */ |
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u64 flags; /* general flags */ |
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/* FFDC data gathering */ |
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struct genwqe_ffdc ffdc[GENWQE_DBG_UNITS]; |
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/* DDCB workqueue */ |
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struct task_struct *card_thread; |
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wait_queue_head_t queue_waitq; |
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struct ddcb_queue queue; /* genwqe DDCB queue */ |
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unsigned int irqs_processed; |
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/* Card health checking thread */ |
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struct task_struct *health_thread; |
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wait_queue_head_t health_waitq; |
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int use_platform_recovery; /* use platform recovery mechanisms */ |
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/* char device */ |
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dev_t devnum_genwqe; /* major/minor num card */ |
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struct class *class_genwqe; /* reference to class object */ |
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struct device *dev; /* for device creation */ |
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struct cdev cdev_genwqe; /* char device for card */ |
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struct dentry *debugfs_root; /* debugfs card root directory */ |
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struct dentry *debugfs_genwqe; /* debugfs driver root directory */ |
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/* pci resources */ |
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struct pci_dev *pci_dev; /* PCI device */ |
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void __iomem *mmio; /* BAR-0 MMIO start */ |
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unsigned long mmio_len; |
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int num_vfs; |
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u32 vf_jobtimeout_msec[GENWQE_MAX_VFS]; |
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int is_privileged; /* access to all regs possible */ |
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/* config regs which we need often */ |
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u64 slu_unitcfg; |
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u64 app_unitcfg; |
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u64 softreset; |
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u64 err_inject; |
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u64 last_gfir; |
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char app_name[5]; |
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spinlock_t file_lock; /* lock for open files */ |
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struct list_head file_list; /* list of open files */ |
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/* debugfs parameters */ |
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int ddcb_software_timeout; /* wait until DDCB times out */ |
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int skip_recovery; /* circumvention if recovery fails */ |
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int kill_timeout; /* wait after sending SIGKILL */ |
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}; |
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/** |
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* enum genwqe_requ_state - State of a DDCB execution request |
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*/ |
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enum genwqe_requ_state { |
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GENWQE_REQU_NEW = 0, |
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GENWQE_REQU_ENQUEUED = 1, |
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GENWQE_REQU_TAPPED = 2, |
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GENWQE_REQU_FINISHED = 3, |
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GENWQE_REQU_STATE_MAX, |
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}; |
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/** |
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* struct genwqe_sgl - Scatter gather list describing user-space memory |
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* @sgl: scatter gather list needs to be 128 byte aligned |
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* @sgl_dma_addr: dma address of sgl |
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* @sgl_size: size of area used for sgl |
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* @user_addr: user-space address of memory area |
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* @user_size: size of user-space memory area |
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* @page: buffer for partial pages if needed |
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* @page_dma_addr: dma address partial pages |
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* @write: should we write it back to userspace? |
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*/ |
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struct genwqe_sgl { |
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dma_addr_t sgl_dma_addr; |
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struct sg_entry *sgl; |
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size_t sgl_size; /* size of sgl */ |
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void __user *user_addr; /* user-space base-address */ |
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size_t user_size; /* size of memory area */ |
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int write; |
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unsigned long nr_pages; |
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unsigned long fpage_offs; |
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size_t fpage_size; |
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size_t lpage_size; |
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void *fpage; |
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dma_addr_t fpage_dma_addr; |
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void *lpage; |
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dma_addr_t lpage_dma_addr; |
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}; |
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int genwqe_alloc_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl, |
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void __user *user_addr, size_t user_size, int write); |
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int genwqe_setup_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl, |
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dma_addr_t *dma_list); |
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int genwqe_free_sync_sgl(struct genwqe_dev *cd, struct genwqe_sgl *sgl); |
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/** |
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* struct ddcb_requ - Kernel internal representation of the DDCB request |
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* @cmd: User space representation of the DDCB execution request |
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*/ |
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struct ddcb_requ { |
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/* kernel specific content */ |
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enum genwqe_requ_state req_state; /* request status */ |
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int num; /* ddcb_no for this request */ |
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struct ddcb_queue *queue; /* associated queue */ |
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struct dma_mapping dma_mappings[DDCB_FIXUPS]; |
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struct genwqe_sgl sgls[DDCB_FIXUPS]; |
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/* kernel/user shared content */ |
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struct genwqe_ddcb_cmd cmd; /* ddcb_no for this request */ |
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struct genwqe_debug_data debug_data; |
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}; |
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/** |
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* struct genwqe_file - Information for open GenWQE devices |
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*/ |
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struct genwqe_file { |
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struct genwqe_dev *cd; |
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struct genwqe_driver *client; |
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struct file *filp; |
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struct fasync_struct *async_queue; |
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struct pid *opener; |
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struct list_head list; /* entry in list of open files */ |
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spinlock_t map_lock; /* lock for dma_mappings */ |
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struct list_head map_list; /* list of dma_mappings */ |
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spinlock_t pin_lock; /* lock for pinned memory */ |
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struct list_head pin_list; /* list of pinned memory */ |
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}; |
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int genwqe_setup_service_layer(struct genwqe_dev *cd); /* for PF only */ |
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int genwqe_finish_queue(struct genwqe_dev *cd); |
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int genwqe_release_service_layer(struct genwqe_dev *cd); |
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/** |
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* genwqe_get_slu_id() - Read Service Layer Unit Id |
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* Return: 0x00: Development code |
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* 0x01: SLC1 (old) |
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* 0x02: SLC2 (sept2012) |
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* 0x03: SLC2 (feb2013, generic driver) |
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*/ |
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static inline int genwqe_get_slu_id(struct genwqe_dev *cd) |
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{ |
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return (int)((cd->slu_unitcfg >> 32) & 0xff); |
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} |
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int genwqe_ddcbs_in_flight(struct genwqe_dev *cd); |
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u8 genwqe_card_type(struct genwqe_dev *cd); |
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int genwqe_card_reset(struct genwqe_dev *cd); |
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int genwqe_set_interrupt_capability(struct genwqe_dev *cd, int count); |
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void genwqe_reset_interrupt_capability(struct genwqe_dev *cd); |
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int genwqe_device_create(struct genwqe_dev *cd); |
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int genwqe_device_remove(struct genwqe_dev *cd); |
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/* debugfs */ |
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void genwqe_init_debugfs(struct genwqe_dev *cd); |
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void genqwe_exit_debugfs(struct genwqe_dev *cd); |
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int genwqe_read_softreset(struct genwqe_dev *cd); |
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/* Hardware Circumventions */ |
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int genwqe_recovery_on_fatal_gfir_required(struct genwqe_dev *cd); |
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int genwqe_flash_readback_fails(struct genwqe_dev *cd); |
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/** |
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* genwqe_write_vreg() - Write register in VF window |
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* @cd: genwqe device |
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* @reg: register address |
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* @val: value to write |
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* @func: 0: PF, 1: VF0, ..., 15: VF14 |
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*/ |
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int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func); |
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/** |
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* genwqe_read_vreg() - Read register in VF window |
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* @cd: genwqe device |
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* @reg: register address |
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* @func: 0: PF, 1: VF0, ..., 15: VF14 |
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* |
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* Return: content of the register |
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*/ |
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u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func); |
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/* FFDC Buffer Management */ |
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int genwqe_ffdc_buff_size(struct genwqe_dev *cd, int unit_id); |
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int genwqe_ffdc_buff_read(struct genwqe_dev *cd, int unit_id, |
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struct genwqe_reg *regs, unsigned int max_regs); |
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int genwqe_read_ffdc_regs(struct genwqe_dev *cd, struct genwqe_reg *regs, |
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unsigned int max_regs, int all); |
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int genwqe_ffdc_dump_dma(struct genwqe_dev *cd, |
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struct genwqe_reg *regs, unsigned int max_regs); |
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int genwqe_init_debug_data(struct genwqe_dev *cd, |
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struct genwqe_debug_data *d); |
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void genwqe_init_crc32(void); |
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int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len); |
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/* Memory allocation/deallocation; dma address handling */ |
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int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, |
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void *uaddr, unsigned long size); |
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int genwqe_user_vunmap(struct genwqe_dev *cd, struct dma_mapping *m); |
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static inline bool dma_mapping_used(struct dma_mapping *m) |
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{ |
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if (!m) |
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return false; |
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return m->size != 0; |
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} |
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|
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/** |
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* __genwqe_execute_ddcb() - Execute DDCB request with addr translation |
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* |
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* This function will do the address translation changes to the DDCBs |
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* according to the definitions required by the ATS field. It looks up |
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* the memory allocation buffer or does vmap/vunmap for the respective |
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* user-space buffers, inclusive page pinning and scatter gather list |
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* buildup and teardown. |
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*/ |
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int __genwqe_execute_ddcb(struct genwqe_dev *cd, |
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struct genwqe_ddcb_cmd *cmd, unsigned int f_flags); |
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|
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/** |
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* __genwqe_execute_raw_ddcb() - Execute DDCB request without addr translation |
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* |
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* This version will not do address translation or any modification of |
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* the DDCB data. It is used e.g. for the MoveFlash DDCB which is |
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* entirely prepared by the driver itself. That means the appropriate |
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* DMA addresses are already in the DDCB and do not need any |
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* modification. |
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*/ |
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int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd, |
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struct genwqe_ddcb_cmd *cmd, |
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unsigned int f_flags); |
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int __genwqe_enqueue_ddcb(struct genwqe_dev *cd, |
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struct ddcb_requ *req, |
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unsigned int f_flags); |
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|
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int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); |
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int __genwqe_purge_ddcb(struct genwqe_dev *cd, struct ddcb_requ *req); |
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|
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/* register access */ |
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int __genwqe_writeq(struct genwqe_dev *cd, u64 byte_offs, u64 val); |
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u64 __genwqe_readq(struct genwqe_dev *cd, u64 byte_offs); |
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int __genwqe_writel(struct genwqe_dev *cd, u64 byte_offs, u32 val); |
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u32 __genwqe_readl(struct genwqe_dev *cd, u64 byte_offs); |
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|
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void *__genwqe_alloc_consistent(struct genwqe_dev *cd, size_t size, |
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dma_addr_t *dma_handle); |
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void __genwqe_free_consistent(struct genwqe_dev *cd, size_t size, |
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void *vaddr, dma_addr_t dma_handle); |
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|
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/* Base clock frequency in MHz */ |
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int genwqe_base_clock_frequency(struct genwqe_dev *cd); |
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|
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/* Before FFDC is captured the traps should be stopped. */ |
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void genwqe_stop_traps(struct genwqe_dev *cd); |
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void genwqe_start_traps(struct genwqe_dev *cd); |
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|
|
/* Hardware circumvention */ |
|
bool genwqe_need_err_masking(struct genwqe_dev *cd); |
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|
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/** |
|
* genwqe_is_privileged() - Determine operation mode for PCI function |
|
* |
|
* On Intel with SRIOV support we see: |
|
* PF: is_physfn = 1 is_virtfn = 0 |
|
* VF: is_physfn = 0 is_virtfn = 1 |
|
* |
|
* On Systems with no SRIOV support _and_ virtualized systems we get: |
|
* is_physfn = 0 is_virtfn = 0 |
|
* |
|
* Other vendors have individual pci device ids to distinguish between |
|
* virtual function drivers and physical function drivers. GenWQE |
|
* unfortunately has just on pci device id for both, VFs and PF. |
|
* |
|
* The following code is used to distinguish if the card is running in |
|
* privileged mode, either as true PF or in a virtualized system with |
|
* full register access e.g. currently on PowerPC. |
|
* |
|
* if (pci_dev->is_virtfn) |
|
* cd->is_privileged = 0; |
|
* else |
|
* cd->is_privileged = (__genwqe_readq(cd, IO_SLU_BITSTREAM) |
|
* != IO_ILLEGAL_VALUE); |
|
*/ |
|
static inline int genwqe_is_privileged(struct genwqe_dev *cd) |
|
{ |
|
return cd->is_privileged; |
|
} |
|
|
|
#endif /* __CARD_BASE_H__ */
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