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530 lines
15 KiB
530 lines
15 KiB
/* |
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* tps80031.c -- TI TPS80031/TPS80032 mfd core driver. |
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* |
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* MFD core driver for TI TPS80031/TPS80032 Fully Integrated |
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* Power Management with Power Path and Battery Charger |
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* |
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* Copyright (c) 2012, NVIDIA Corporation. |
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* |
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* Author: Laxman Dewangan <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, |
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* whether express or implied; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
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* 02111-1307, USA |
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*/ |
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|
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#include <linux/err.h> |
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#include <linux/i2c.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/mfd/core.h> |
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#include <linux/mfd/tps80031.h> |
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#include <linux/pm.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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static const struct resource tps80031_rtc_resources[] = { |
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{ |
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.start = TPS80031_INT_RTC_ALARM, |
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.end = TPS80031_INT_RTC_ALARM, |
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.flags = IORESOURCE_IRQ, |
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}, |
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}; |
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|
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/* TPS80031 sub mfd devices */ |
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static const struct mfd_cell tps80031_cell[] = { |
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{ |
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.name = "tps80031-pmic", |
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}, |
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{ |
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.name = "tps80031-clock", |
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}, |
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{ |
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.name = "tps80031-rtc", |
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.num_resources = ARRAY_SIZE(tps80031_rtc_resources), |
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.resources = tps80031_rtc_resources, |
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}, |
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{ |
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.name = "tps80031-gpadc", |
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}, |
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{ |
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.name = "tps80031-fuel-gauge", |
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}, |
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{ |
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.name = "tps80031-charger", |
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}, |
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}; |
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static int tps80031_slave_address[TPS80031_NUM_SLAVES] = { |
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TPS80031_I2C_ID0_ADDR, |
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TPS80031_I2C_ID1_ADDR, |
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TPS80031_I2C_ID2_ADDR, |
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TPS80031_I2C_ID3_ADDR, |
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}; |
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struct tps80031_pupd_data { |
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u8 reg; |
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u8 pullup_bit; |
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u8 pulldown_bit; |
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}; |
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|
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#define TPS80031_IRQ(_reg, _mask) \ |
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{ \ |
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.reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \ |
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TPS80031_INT_MSK_LINE_A, \ |
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.mask = BIT(_mask), \ |
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} |
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static const struct regmap_irq tps80031_main_irqs[] = { |
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[TPS80031_INT_PWRON] = TPS80031_IRQ(A, 0), |
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[TPS80031_INT_RPWRON] = TPS80031_IRQ(A, 1), |
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[TPS80031_INT_SYS_VLOW] = TPS80031_IRQ(A, 2), |
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[TPS80031_INT_RTC_ALARM] = TPS80031_IRQ(A, 3), |
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[TPS80031_INT_RTC_PERIOD] = TPS80031_IRQ(A, 4), |
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[TPS80031_INT_HOT_DIE] = TPS80031_IRQ(A, 5), |
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[TPS80031_INT_VXX_SHORT] = TPS80031_IRQ(A, 6), |
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[TPS80031_INT_SPDURATION] = TPS80031_IRQ(A, 7), |
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[TPS80031_INT_WATCHDOG] = TPS80031_IRQ(B, 0), |
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[TPS80031_INT_BAT] = TPS80031_IRQ(B, 1), |
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[TPS80031_INT_SIM] = TPS80031_IRQ(B, 2), |
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[TPS80031_INT_MMC] = TPS80031_IRQ(B, 3), |
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[TPS80031_INT_RES] = TPS80031_IRQ(B, 4), |
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[TPS80031_INT_GPADC_RT] = TPS80031_IRQ(B, 5), |
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[TPS80031_INT_GPADC_SW2_EOC] = TPS80031_IRQ(B, 6), |
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[TPS80031_INT_CC_AUTOCAL] = TPS80031_IRQ(B, 7), |
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[TPS80031_INT_ID_WKUP] = TPS80031_IRQ(C, 0), |
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[TPS80031_INT_VBUSS_WKUP] = TPS80031_IRQ(C, 1), |
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[TPS80031_INT_ID] = TPS80031_IRQ(C, 2), |
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[TPS80031_INT_VBUS] = TPS80031_IRQ(C, 3), |
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[TPS80031_INT_CHRG_CTRL] = TPS80031_IRQ(C, 4), |
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[TPS80031_INT_EXT_CHRG] = TPS80031_IRQ(C, 5), |
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[TPS80031_INT_INT_CHRG] = TPS80031_IRQ(C, 6), |
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[TPS80031_INT_RES2] = TPS80031_IRQ(C, 7), |
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}; |
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static struct regmap_irq_chip tps80031_irq_chip = { |
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.name = "tps80031", |
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.irqs = tps80031_main_irqs, |
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.num_irqs = ARRAY_SIZE(tps80031_main_irqs), |
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.num_regs = 3, |
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.status_base = TPS80031_INT_STS_A, |
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.mask_base = TPS80031_INT_MSK_LINE_A, |
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}; |
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#define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \ |
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{ \ |
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.reg = TPS80031_CFG_INPUT_PUPD##_reg, \ |
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.pulldown_bit = _pulldown_bit, \ |
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.pullup_bit = _pullup_bit, \ |
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} |
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static const struct tps80031_pupd_data tps80031_pupds[] = { |
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[TPS80031_PREQ1] = PUPD_DATA(1, BIT(0), BIT(1)), |
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[TPS80031_PREQ2A] = PUPD_DATA(1, BIT(2), BIT(3)), |
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[TPS80031_PREQ2B] = PUPD_DATA(1, BIT(4), BIT(5)), |
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[TPS80031_PREQ2C] = PUPD_DATA(1, BIT(6), BIT(7)), |
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[TPS80031_PREQ3] = PUPD_DATA(2, BIT(0), BIT(1)), |
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[TPS80031_NRES_WARM] = PUPD_DATA(2, 0, BIT(2)), |
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[TPS80031_PWM_FORCE] = PUPD_DATA(2, BIT(5), 0), |
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[TPS80031_CHRG_EXT_CHRG_STATZ] = PUPD_DATA(2, 0, BIT(6)), |
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[TPS80031_SIM] = PUPD_DATA(3, BIT(0), BIT(1)), |
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[TPS80031_MMC] = PUPD_DATA(3, BIT(2), BIT(3)), |
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[TPS80031_GPADC_START] = PUPD_DATA(3, BIT(4), 0), |
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[TPS80031_DVSI2C_SCL] = PUPD_DATA(4, 0, BIT(0)), |
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[TPS80031_DVSI2C_SDA] = PUPD_DATA(4, 0, BIT(1)), |
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[TPS80031_CTLI2C_SCL] = PUPD_DATA(4, 0, BIT(2)), |
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[TPS80031_CTLI2C_SDA] = PUPD_DATA(4, 0, BIT(3)), |
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}; |
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static struct tps80031 *tps80031_power_off_dev; |
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int tps80031_ext_power_req_config(struct device *dev, |
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unsigned long ext_ctrl_flag, int preq_bit, |
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int state_reg_add, int trans_reg_add) |
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{ |
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u8 res_ass_reg = 0; |
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int preq_mask_bit = 0; |
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int ret; |
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if (!(ext_ctrl_flag & TPS80031_EXT_PWR_REQ)) |
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return 0; |
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if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ1) { |
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res_ass_reg = TPS80031_PREQ1_RES_ASS_A + (preq_bit >> 3); |
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preq_mask_bit = 5; |
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} else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ2) { |
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res_ass_reg = TPS80031_PREQ2_RES_ASS_A + (preq_bit >> 3); |
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preq_mask_bit = 6; |
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} else if (ext_ctrl_flag & TPS80031_PWR_REQ_INPUT_PREQ3) { |
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res_ass_reg = TPS80031_PREQ3_RES_ASS_A + (preq_bit >> 3); |
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preq_mask_bit = 7; |
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} |
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/* Configure REQ_ASS registers */ |
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ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, res_ass_reg, |
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BIT(preq_bit & 0x7)); |
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if (ret < 0) { |
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dev_err(dev, "reg 0x%02x setbit failed, err = %d\n", |
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res_ass_reg, ret); |
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return ret; |
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} |
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/* Unmask the PREQ */ |
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ret = tps80031_clr_bits(dev, TPS80031_SLAVE_ID1, |
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TPS80031_PHOENIX_MSK_TRANSITION, BIT(preq_mask_bit)); |
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if (ret < 0) { |
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dev_err(dev, "reg 0x%02x clrbit failed, err = %d\n", |
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TPS80031_PHOENIX_MSK_TRANSITION, ret); |
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return ret; |
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} |
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/* Switch regulator control to resource now */ |
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if (ext_ctrl_flag & (TPS80031_PWR_REQ_INPUT_PREQ2 | |
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TPS80031_PWR_REQ_INPUT_PREQ3)) { |
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ret = tps80031_update(dev, TPS80031_SLAVE_ID1, state_reg_add, |
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0x0, TPS80031_STATE_MASK); |
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if (ret < 0) |
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dev_err(dev, "reg 0x%02x update failed, err = %d\n", |
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state_reg_add, ret); |
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} else { |
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ret = tps80031_update(dev, TPS80031_SLAVE_ID1, trans_reg_add, |
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TPS80031_TRANS_SLEEP_OFF, |
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TPS80031_TRANS_SLEEP_MASK); |
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if (ret < 0) |
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dev_err(dev, "reg 0x%02x update failed, err = %d\n", |
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trans_reg_add, ret); |
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} |
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(tps80031_ext_power_req_config); |
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static void tps80031_power_off(void) |
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{ |
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dev_info(tps80031_power_off_dev->dev, "switching off PMU\n"); |
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tps80031_write(tps80031_power_off_dev->dev, TPS80031_SLAVE_ID1, |
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TPS80031_PHOENIX_DEV_ON, TPS80031_DEVOFF); |
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} |
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static void tps80031_pupd_init(struct tps80031 *tps80031, |
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struct tps80031_platform_data *pdata) |
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{ |
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struct tps80031_pupd_init_data *pupd_init_data = pdata->pupd_init_data; |
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int data_size = pdata->pupd_init_data_size; |
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int i; |
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for (i = 0; i < data_size; ++i) { |
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struct tps80031_pupd_init_data *pupd_init = &pupd_init_data[i]; |
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const struct tps80031_pupd_data *pupd = |
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&tps80031_pupds[pupd_init->input_pin]; |
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u8 update_value = 0; |
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u8 update_mask = pupd->pulldown_bit | pupd->pullup_bit; |
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if (pupd_init->setting == TPS80031_PUPD_PULLDOWN) |
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update_value = pupd->pulldown_bit; |
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else if (pupd_init->setting == TPS80031_PUPD_PULLUP) |
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update_value = pupd->pullup_bit; |
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tps80031_update(tps80031->dev, TPS80031_SLAVE_ID1, pupd->reg, |
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update_value, update_mask); |
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} |
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} |
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static int tps80031_init_ext_control(struct tps80031 *tps80031, |
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struct tps80031_platform_data *pdata) |
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{ |
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struct device *dev = tps80031->dev; |
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int ret; |
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int i; |
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|
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/* Clear all external control for this rail */ |
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for (i = 0; i < 9; ++i) { |
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ret = tps80031_write(dev, TPS80031_SLAVE_ID1, |
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TPS80031_PREQ1_RES_ASS_A + i, 0); |
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if (ret < 0) { |
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dev_err(dev, "reg 0x%02x write failed, err = %d\n", |
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TPS80031_PREQ1_RES_ASS_A + i, ret); |
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return ret; |
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} |
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} |
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/* Mask the PREQ */ |
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ret = tps80031_set_bits(dev, TPS80031_SLAVE_ID1, |
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TPS80031_PHOENIX_MSK_TRANSITION, 0x7 << 5); |
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if (ret < 0) { |
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dev_err(dev, "reg 0x%02x set_bits failed, err = %d\n", |
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TPS80031_PHOENIX_MSK_TRANSITION, ret); |
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return ret; |
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} |
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return ret; |
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} |
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static int tps80031_irq_init(struct tps80031 *tps80031, int irq, int irq_base) |
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{ |
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struct device *dev = tps80031->dev; |
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int i, ret; |
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/* |
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* The MASK register used for updating status register when |
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* interrupt occurs and LINE register used to pass the status |
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* to actual interrupt line. As per datasheet: |
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* When INT_MSK_LINE [i] is set to 1, the associated interrupt |
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* number i is INT line masked, which means that no interrupt is |
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* generated on the INT line. |
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* When INT_MSK_LINE [i] is set to 0, the associated interrupt |
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* number i is line enabled: An interrupt is generated on the |
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* INT line. |
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* In any case, the INT_STS [i] status bit may or may not be updated, |
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* only linked to the INT_MSK_STS [i] configuration register bit. |
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* |
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* When INT_MSK_STS [i] is set to 1, the associated interrupt number |
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* i is status masked, which means that no interrupt is stored in |
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* the INT_STS[i] status bit. Note that no interrupt number i is |
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* generated on the INT line, even if the INT_MSK_LINE [i] register |
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* bit is set to 0. |
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* When INT_MSK_STS [i] is set to 0, the associated interrupt number i |
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* is status enabled: An interrupt status is updated in the INT_STS [i] |
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* register. The interrupt may or may not be generated on the INT line, |
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* depending on the INT_MSK_LINE [i] configuration register bit. |
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*/ |
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for (i = 0; i < 3; i++) |
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tps80031_write(dev, TPS80031_SLAVE_ID2, |
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TPS80031_INT_MSK_STS_A + i, 0x00); |
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ret = regmap_add_irq_chip(tps80031->regmap[TPS80031_SLAVE_ID2], irq, |
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IRQF_ONESHOT, irq_base, |
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&tps80031_irq_chip, &tps80031->irq_data); |
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if (ret < 0) { |
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dev_err(dev, "add irq failed, err = %d\n", ret); |
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return ret; |
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} |
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return ret; |
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} |
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static bool rd_wr_reg_id0(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TPS80031_SMPS1_CFG_FORCE ... TPS80031_SMPS2_CFG_VOLTAGE: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool rd_wr_reg_id1(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TPS80031_SECONDS_REG ... TPS80031_RTC_RESET_STATUS_REG: |
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case TPS80031_VALIDITY0 ... TPS80031_VALIDITY7: |
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case TPS80031_PHOENIX_START_CONDITION ... TPS80031_KEY_PRESS_DUR_CFG: |
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case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE: |
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case TPS80031_BROADCAST_ADDR_ALL ... TPS80031_BROADCAST_ADDR_CLK_RST: |
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case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE: |
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case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE: |
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case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C: |
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case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING: |
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case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD: |
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case TPS80031_BACKUP_REG: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool is_volatile_reg_id1(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TPS80031_SMPS4_CFG_TRANS ... TPS80031_SMPS3_CFG_VOLTAGE: |
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case TPS80031_VANA_CFG_TRANS ... TPS80031_LDO7_CFG_VOLTAGE: |
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case TPS80031_REGEN1_CFG_TRANS ... TPS80031_TMP_CFG_STATE: |
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case TPS80031_PREQ1_RES_ASS_A ... TPS80031_PREQ3_RES_ASS_C: |
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case TPS80031_SMPS_OFFSET ... TPS80031_BATDEBOUNCING: |
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case TPS80031_CFG_INPUT_PUPD1 ... TPS80031_CFG_SMPS_PD: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool rd_wr_reg_id2(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TPS80031_USB_VENDOR_ID_LSB ... TPS80031_USB_OTG_REVISION: |
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case TPS80031_GPADC_CTRL ... TPS80031_CTRL_P1: |
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case TPS80031_RTCH0_LSB ... TPS80031_GPCH0_MSB: |
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case TPS80031_TOGGLE1 ... TPS80031_VIBMODE: |
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case TPS80031_PWM1ON ... TPS80031_PWM2OFF: |
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case TPS80031_FG_REG_00 ... TPS80031_FG_REG_11: |
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case TPS80031_INT_STS_A ... TPS80031_INT_MSK_STS_C: |
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case TPS80031_CONTROLLER_CTRL2 ... TPS80031_LED_PWM_CTRL2: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool rd_wr_reg_id3(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case TPS80031_GPADC_TRIM0 ... TPS80031_GPADC_TRIM18: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static const struct regmap_config tps80031_regmap_configs[] = { |
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{ |
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.reg_bits = 8, |
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.val_bits = 8, |
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.writeable_reg = rd_wr_reg_id0, |
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.readable_reg = rd_wr_reg_id0, |
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.max_register = TPS80031_MAX_REGISTER, |
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}, |
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{ |
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.reg_bits = 8, |
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.val_bits = 8, |
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.writeable_reg = rd_wr_reg_id1, |
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.readable_reg = rd_wr_reg_id1, |
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.volatile_reg = is_volatile_reg_id1, |
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.max_register = TPS80031_MAX_REGISTER, |
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}, |
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{ |
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.reg_bits = 8, |
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.val_bits = 8, |
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.writeable_reg = rd_wr_reg_id2, |
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.readable_reg = rd_wr_reg_id2, |
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.max_register = TPS80031_MAX_REGISTER, |
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}, |
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{ |
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.reg_bits = 8, |
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.val_bits = 8, |
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.writeable_reg = rd_wr_reg_id3, |
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.readable_reg = rd_wr_reg_id3, |
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.max_register = TPS80031_MAX_REGISTER, |
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}, |
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}; |
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static int tps80031_probe(struct i2c_client *client, |
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const struct i2c_device_id *id) |
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{ |
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struct tps80031_platform_data *pdata = dev_get_platdata(&client->dev); |
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struct tps80031 *tps80031; |
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int ret; |
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uint8_t es_version; |
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uint8_t ep_ver; |
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int i; |
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|
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if (!pdata) { |
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dev_err(&client->dev, "tps80031 requires platform data\n"); |
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return -EINVAL; |
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} |
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tps80031 = devm_kzalloc(&client->dev, sizeof(*tps80031), GFP_KERNEL); |
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if (!tps80031) |
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return -ENOMEM; |
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|
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for (i = 0; i < TPS80031_NUM_SLAVES; i++) { |
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if (tps80031_slave_address[i] == client->addr) |
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tps80031->clients[i] = client; |
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else |
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tps80031->clients[i] = devm_i2c_new_dummy_device(&client->dev, |
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client->adapter, tps80031_slave_address[i]); |
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if (IS_ERR(tps80031->clients[i])) { |
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dev_err(&client->dev, "can't attach client %d\n", i); |
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return PTR_ERR(tps80031->clients[i]); |
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} |
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|
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i2c_set_clientdata(tps80031->clients[i], tps80031); |
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tps80031->regmap[i] = devm_regmap_init_i2c(tps80031->clients[i], |
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&tps80031_regmap_configs[i]); |
|
if (IS_ERR(tps80031->regmap[i])) { |
|
ret = PTR_ERR(tps80031->regmap[i]); |
|
dev_err(&client->dev, |
|
"regmap %d init failed, err %d\n", i, ret); |
|
return ret; |
|
} |
|
} |
|
|
|
ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3, |
|
TPS80031_JTAGVERNUM, &es_version); |
|
if (ret < 0) { |
|
dev_err(&client->dev, |
|
"Silicon version number read failed: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = tps80031_read(&client->dev, TPS80031_SLAVE_ID3, |
|
TPS80031_EPROM_REV, &ep_ver); |
|
if (ret < 0) { |
|
dev_err(&client->dev, |
|
"Silicon eeprom version read failed: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
dev_info(&client->dev, "ES version 0x%02x and EPROM version 0x%02x\n", |
|
es_version, ep_ver); |
|
tps80031->es_version = es_version; |
|
tps80031->dev = &client->dev; |
|
i2c_set_clientdata(client, tps80031); |
|
tps80031->chip_info = id->driver_data; |
|
|
|
ret = tps80031_irq_init(tps80031, client->irq, pdata->irq_base); |
|
if (ret) { |
|
dev_err(&client->dev, "IRQ init failed: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
tps80031_pupd_init(tps80031, pdata); |
|
|
|
tps80031_init_ext_control(tps80031, pdata); |
|
|
|
ret = mfd_add_devices(tps80031->dev, -1, |
|
tps80031_cell, ARRAY_SIZE(tps80031_cell), |
|
NULL, 0, |
|
regmap_irq_get_domain(tps80031->irq_data)); |
|
if (ret < 0) { |
|
dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret); |
|
goto fail_mfd_add; |
|
} |
|
|
|
if (pdata->use_power_off && !pm_power_off) { |
|
tps80031_power_off_dev = tps80031; |
|
pm_power_off = tps80031_power_off; |
|
} |
|
return 0; |
|
|
|
fail_mfd_add: |
|
regmap_del_irq_chip(client->irq, tps80031->irq_data); |
|
return ret; |
|
} |
|
|
|
static const struct i2c_device_id tps80031_id_table[] = { |
|
{ "tps80031", TPS80031 }, |
|
{ "tps80032", TPS80032 }, |
|
{ } |
|
}; |
|
|
|
static struct i2c_driver tps80031_driver = { |
|
.driver = { |
|
.name = "tps80031", |
|
.suppress_bind_attrs = true, |
|
}, |
|
.probe = tps80031_probe, |
|
.id_table = tps80031_id_table, |
|
}; |
|
|
|
static int __init tps80031_init(void) |
|
{ |
|
return i2c_add_driver(&tps80031_driver); |
|
} |
|
subsys_initcall(tps80031_init);
|
|
|