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130 lines
2.8 KiB
130 lines
2.8 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* timberdale.h timberdale FPGA MFD driver defines |
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* Copyright (c) 2009 Intel Corporation |
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*/ |
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/* Supports: |
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* Timberdale FPGA |
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*/ |
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#ifndef MFD_TIMBERDALE_H |
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#define MFD_TIMBERDALE_H |
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#define DRV_VERSION "0.3" |
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/* This driver only support versions >= 3.8 and < 4.0 */ |
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#define TIMB_SUPPORTED_MAJOR 3 |
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/* This driver only support minor >= 8 */ |
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#define TIMB_REQUIRED_MINOR 8 |
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/* Registers of the control area */ |
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#define TIMB_REV_MAJOR 0x00 |
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#define TIMB_REV_MINOR 0x04 |
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#define TIMB_HW_CONFIG 0x08 |
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#define TIMB_SW_RST 0x40 |
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/* bits in the TIMB_HW_CONFIG register */ |
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#define TIMB_HW_CONFIG_SPI_8BIT 0x80 |
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#define TIMB_HW_VER_MASK 0x0f |
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#define TIMB_HW_VER0 0x00 |
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#define TIMB_HW_VER1 0x01 |
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#define TIMB_HW_VER2 0x02 |
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#define TIMB_HW_VER3 0x03 |
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#define OCORESOFFSET 0x0 |
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#define OCORESEND 0x1f |
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#define SPIOFFSET 0x80 |
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#define SPIEND 0xff |
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#define UARTLITEOFFSET 0x100 |
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#define UARTLITEEND 0x10f |
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#define RDSOFFSET 0x180 |
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#define RDSEND 0x183 |
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#define ETHOFFSET 0x300 |
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#define ETHEND 0x3ff |
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#define GPIOOFFSET 0x400 |
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#define GPIOEND 0x7ff |
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#define CHIPCTLOFFSET 0x800 |
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#define CHIPCTLEND 0x8ff |
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#define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET + 1) |
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#define INTCOFFSET 0xc00 |
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#define INTCEND 0xfff |
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#define INTCSIZE (INTCEND - INTCOFFSET) |
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#define MOSTOFFSET 0x1000 |
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#define MOSTEND 0x13ff |
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#define UARTOFFSET 0x1400 |
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#define UARTEND 0x17ff |
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#define XIICOFFSET 0x1800 |
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#define XIICEND 0x19ff |
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#define I2SOFFSET 0x1C00 |
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#define I2SEND 0x1fff |
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#define LOGIWOFFSET 0x30000 |
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#define LOGIWEND 0x37fff |
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#define MLCOREOFFSET 0x40000 |
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#define MLCOREEND 0x43fff |
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#define DMAOFFSET 0x01000000 |
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#define DMAEND 0x013fffff |
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/* SDHC0 is placed in PCI bar 1 */ |
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#define SDHC0OFFSET 0x00 |
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#define SDHC0END 0xff |
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/* SDHC1 is placed in PCI bar 2 */ |
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#define SDHC1OFFSET 0x00 |
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#define SDHC1END 0xff |
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#define PCI_VENDOR_ID_TIMB 0x10ee |
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#define PCI_DEVICE_ID_TIMB 0xa123 |
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#define IRQ_TIMBERDALE_INIC 0 |
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#define IRQ_TIMBERDALE_MLB 1 |
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#define IRQ_TIMBERDALE_GPIO 2 |
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#define IRQ_TIMBERDALE_I2C 3 |
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#define IRQ_TIMBERDALE_UART 4 |
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#define IRQ_TIMBERDALE_DMA 5 |
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#define IRQ_TIMBERDALE_I2S 6 |
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#define IRQ_TIMBERDALE_TSC_INT 7 |
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#define IRQ_TIMBERDALE_SDHC 8 |
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#define IRQ_TIMBERDALE_ADV7180 9 |
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#define IRQ_TIMBERDALE_ETHSW_IF 10 |
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#define IRQ_TIMBERDALE_SPI 11 |
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#define IRQ_TIMBERDALE_UARTLITE 12 |
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#define IRQ_TIMBERDALE_MLCORE 13 |
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#define IRQ_TIMBERDALE_MLCORE_BUF 14 |
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#define IRQ_TIMBERDALE_RDS 15 |
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#define TIMBERDALE_NR_IRQS 16 |
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#define GPIO_PIN_ASCB 8 |
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#define GPIO_PIN_INIC_RST 14 |
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#define GPIO_PIN_BT_RST 15 |
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#define GPIO_NR_PINS 16 |
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/* DMA Channels */ |
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#define DMA_UART_RX 0 |
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#define DMA_UART_TX 1 |
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#define DMA_MLB_RX 2 |
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#define DMA_MLB_TX 3 |
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#define DMA_VIDEO_RX 4 |
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#define DMA_VIDEO_DROP 5 |
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#define DMA_SDHCI_RX 6 |
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#define DMA_SDHCI_TX 7 |
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#define DMA_ETH_RX 8 |
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#define DMA_ETH_TX 9 |
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#endif
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