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1605 lines
27 KiB
1605 lines
27 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. |
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*/ |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#if defined(CONFIG_ARCH_TEGRA_186_SOC) |
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#include <dt-bindings/memory/tegra186-mc.h> |
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#endif |
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#if defined(CONFIG_ARCH_TEGRA_194_SOC) |
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#include <dt-bindings/memory/tegra194-mc.h> |
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#endif |
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struct tegra186_mc_client { |
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const char *name; |
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unsigned int sid; |
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struct { |
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unsigned int override; |
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unsigned int security; |
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} regs; |
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}; |
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struct tegra186_mc_soc { |
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const struct tegra186_mc_client *clients; |
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unsigned int num_clients; |
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}; |
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struct tegra186_mc { |
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struct device *dev; |
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void __iomem *regs; |
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const struct tegra186_mc_soc *soc; |
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}; |
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static void tegra186_mc_program_sid(struct tegra186_mc *mc) |
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{ |
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unsigned int i; |
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for (i = 0; i < mc->soc->num_clients; i++) { |
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const struct tegra186_mc_client *client = &mc->soc->clients[i]; |
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u32 override, security; |
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override = readl(mc->regs + client->regs.override); |
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security = readl(mc->regs + client->regs.security); |
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dev_dbg(mc->dev, "client %s: override: %x security: %x\n", |
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client->name, override, security); |
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dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid, |
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client->name); |
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writel(client->sid, mc->regs + client->regs.override); |
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override = readl(mc->regs + client->regs.override); |
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security = readl(mc->regs + client->regs.security); |
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dev_dbg(mc->dev, "client %s: override: %x security: %x\n", |
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client->name, override, security); |
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} |
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} |
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#if defined(CONFIG_ARCH_TEGRA_186_SOC) |
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static const struct tegra186_mc_client tegra186_mc_clients[] = { |
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{ |
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.name = "ptcr", |
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.sid = TEGRA186_SID_PASSTHROUGH, |
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.regs = { |
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.override = 0x000, |
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.security = 0x004, |
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}, |
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}, { |
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.name = "afir", |
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.sid = TEGRA186_SID_AFI, |
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.regs = { |
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.override = 0x070, |
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.security = 0x074, |
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}, |
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}, { |
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.name = "hdar", |
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.sid = TEGRA186_SID_HDA, |
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.regs = { |
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.override = 0x0a8, |
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.security = 0x0ac, |
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}, |
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}, { |
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.name = "host1xdmar", |
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.sid = TEGRA186_SID_HOST1X, |
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.regs = { |
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.override = 0x0b0, |
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.security = 0x0b4, |
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}, |
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}, { |
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.name = "nvencsrd", |
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.sid = TEGRA186_SID_NVENC, |
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.regs = { |
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.override = 0x0e0, |
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.security = 0x0e4, |
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}, |
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}, { |
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.name = "satar", |
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.sid = TEGRA186_SID_SATA, |
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.regs = { |
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.override = 0x0f8, |
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.security = 0x0fc, |
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}, |
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}, { |
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.name = "mpcorer", |
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.sid = TEGRA186_SID_PASSTHROUGH, |
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.regs = { |
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.override = 0x138, |
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.security = 0x13c, |
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}, |
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}, { |
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.name = "nvencswr", |
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.sid = TEGRA186_SID_NVENC, |
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.regs = { |
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.override = 0x158, |
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.security = 0x15c, |
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}, |
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}, { |
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.name = "afiw", |
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.sid = TEGRA186_SID_AFI, |
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.regs = { |
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.override = 0x188, |
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.security = 0x18c, |
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}, |
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}, { |
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.name = "hdaw", |
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.sid = TEGRA186_SID_HDA, |
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.regs = { |
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.override = 0x1a8, |
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.security = 0x1ac, |
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}, |
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}, { |
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.name = "mpcorew", |
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.sid = TEGRA186_SID_PASSTHROUGH, |
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.regs = { |
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.override = 0x1c8, |
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.security = 0x1cc, |
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}, |
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}, { |
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.name = "sataw", |
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.sid = TEGRA186_SID_SATA, |
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.regs = { |
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.override = 0x1e8, |
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.security = 0x1ec, |
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}, |
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}, { |
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.name = "ispra", |
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.sid = TEGRA186_SID_ISP, |
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.regs = { |
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.override = 0x220, |
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.security = 0x224, |
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}, |
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}, { |
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.name = "ispwa", |
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.sid = TEGRA186_SID_ISP, |
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.regs = { |
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.override = 0x230, |
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.security = 0x234, |
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}, |
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}, { |
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.name = "ispwb", |
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.sid = TEGRA186_SID_ISP, |
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.regs = { |
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.override = 0x238, |
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.security = 0x23c, |
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}, |
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}, { |
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.name = "xusb_hostr", |
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.sid = TEGRA186_SID_XUSB_HOST, |
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.regs = { |
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.override = 0x250, |
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.security = 0x254, |
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}, |
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}, { |
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.name = "xusb_hostw", |
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.sid = TEGRA186_SID_XUSB_HOST, |
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.regs = { |
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.override = 0x258, |
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.security = 0x25c, |
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}, |
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}, { |
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.name = "xusb_devr", |
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.sid = TEGRA186_SID_XUSB_DEV, |
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.regs = { |
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.override = 0x260, |
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.security = 0x264, |
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}, |
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}, { |
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.name = "xusb_devw", |
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.sid = TEGRA186_SID_XUSB_DEV, |
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.regs = { |
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.override = 0x268, |
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.security = 0x26c, |
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}, |
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}, { |
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.name = "tsecsrd", |
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.sid = TEGRA186_SID_TSEC, |
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.regs = { |
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.override = 0x2a0, |
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.security = 0x2a4, |
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}, |
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}, { |
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.name = "tsecswr", |
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.sid = TEGRA186_SID_TSEC, |
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.regs = { |
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.override = 0x2a8, |
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.security = 0x2ac, |
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}, |
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}, { |
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.name = "gpusrd", |
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.sid = TEGRA186_SID_GPU, |
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.regs = { |
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.override = 0x2c0, |
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.security = 0x2c4, |
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}, |
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}, { |
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.name = "gpuswr", |
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.sid = TEGRA186_SID_GPU, |
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.regs = { |
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.override = 0x2c8, |
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.security = 0x2cc, |
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}, |
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}, { |
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.name = "sdmmcra", |
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.sid = TEGRA186_SID_SDMMC1, |
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.regs = { |
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.override = 0x300, |
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.security = 0x304, |
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}, |
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}, { |
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.name = "sdmmcraa", |
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.sid = TEGRA186_SID_SDMMC2, |
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.regs = { |
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.override = 0x308, |
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.security = 0x30c, |
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}, |
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}, { |
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.name = "sdmmcr", |
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.sid = TEGRA186_SID_SDMMC3, |
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.regs = { |
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.override = 0x310, |
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.security = 0x314, |
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}, |
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}, { |
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.name = "sdmmcrab", |
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.sid = TEGRA186_SID_SDMMC4, |
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.regs = { |
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.override = 0x318, |
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.security = 0x31c, |
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}, |
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}, { |
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.name = "sdmmcwa", |
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.sid = TEGRA186_SID_SDMMC1, |
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.regs = { |
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.override = 0x320, |
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.security = 0x324, |
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}, |
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}, { |
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.name = "sdmmcwaa", |
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.sid = TEGRA186_SID_SDMMC2, |
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.regs = { |
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.override = 0x328, |
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.security = 0x32c, |
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}, |
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}, { |
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.name = "sdmmcw", |
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.sid = TEGRA186_SID_SDMMC3, |
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.regs = { |
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.override = 0x330, |
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.security = 0x334, |
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}, |
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}, { |
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.name = "sdmmcwab", |
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.sid = TEGRA186_SID_SDMMC4, |
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.regs = { |
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.override = 0x338, |
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.security = 0x33c, |
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}, |
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}, { |
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.name = "vicsrd", |
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.sid = TEGRA186_SID_VIC, |
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.regs = { |
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.override = 0x360, |
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.security = 0x364, |
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}, |
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}, { |
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.name = "vicswr", |
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.sid = TEGRA186_SID_VIC, |
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.regs = { |
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.override = 0x368, |
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.security = 0x36c, |
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}, |
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}, { |
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.name = "viw", |
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.sid = TEGRA186_SID_VI, |
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.regs = { |
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.override = 0x390, |
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.security = 0x394, |
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}, |
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}, { |
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.name = "nvdecsrd", |
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.sid = TEGRA186_SID_NVDEC, |
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.regs = { |
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.override = 0x3c0, |
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.security = 0x3c4, |
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}, |
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}, { |
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.name = "nvdecswr", |
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.sid = TEGRA186_SID_NVDEC, |
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.regs = { |
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.override = 0x3c8, |
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.security = 0x3cc, |
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}, |
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}, { |
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.name = "aper", |
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.sid = TEGRA186_SID_APE, |
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.regs = { |
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.override = 0x3d0, |
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.security = 0x3d4, |
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}, |
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}, { |
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.name = "apew", |
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.sid = TEGRA186_SID_APE, |
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.regs = { |
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.override = 0x3d8, |
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.security = 0x3dc, |
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}, |
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}, { |
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.name = "nvjpgsrd", |
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.sid = TEGRA186_SID_NVJPG, |
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.regs = { |
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.override = 0x3f0, |
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.security = 0x3f4, |
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}, |
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}, { |
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.name = "nvjpgswr", |
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.sid = TEGRA186_SID_NVJPG, |
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.regs = { |
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.override = 0x3f8, |
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.security = 0x3fc, |
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}, |
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}, { |
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.name = "sesrd", |
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.sid = TEGRA186_SID_SE, |
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.regs = { |
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.override = 0x400, |
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.security = 0x404, |
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}, |
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}, { |
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.name = "seswr", |
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.sid = TEGRA186_SID_SE, |
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.regs = { |
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.override = 0x408, |
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.security = 0x40c, |
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}, |
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}, { |
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.name = "etrr", |
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.sid = TEGRA186_SID_ETR, |
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.regs = { |
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.override = 0x420, |
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.security = 0x424, |
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}, |
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}, { |
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.name = "etrw", |
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.sid = TEGRA186_SID_ETR, |
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.regs = { |
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.override = 0x428, |
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.security = 0x42c, |
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}, |
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}, { |
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.name = "tsecsrdb", |
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.sid = TEGRA186_SID_TSECB, |
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.regs = { |
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.override = 0x430, |
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.security = 0x434, |
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}, |
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}, { |
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.name = "tsecswrb", |
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.sid = TEGRA186_SID_TSECB, |
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.regs = { |
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.override = 0x438, |
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.security = 0x43c, |
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}, |
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}, { |
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.name = "gpusrd2", |
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.sid = TEGRA186_SID_GPU, |
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.regs = { |
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.override = 0x440, |
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.security = 0x444, |
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}, |
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}, { |
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.name = "gpuswr2", |
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.sid = TEGRA186_SID_GPU, |
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.regs = { |
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.override = 0x448, |
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.security = 0x44c, |
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}, |
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}, { |
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.name = "axisr", |
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.sid = TEGRA186_SID_GPCDMA_0, |
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.regs = { |
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.override = 0x460, |
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.security = 0x464, |
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}, |
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}, { |
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.name = "axisw", |
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.sid = TEGRA186_SID_GPCDMA_0, |
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.regs = { |
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.override = 0x468, |
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.security = 0x46c, |
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}, |
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}, { |
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.name = "eqosr", |
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.sid = TEGRA186_SID_EQOS, |
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.regs = { |
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.override = 0x470, |
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.security = 0x474, |
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}, |
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}, { |
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.name = "eqosw", |
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.sid = TEGRA186_SID_EQOS, |
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.regs = { |
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.override = 0x478, |
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.security = 0x47c, |
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}, |
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}, { |
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.name = "ufshcr", |
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.sid = TEGRA186_SID_UFSHC, |
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.regs = { |
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.override = 0x480, |
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.security = 0x484, |
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}, |
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}, { |
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.name = "ufshcw", |
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.sid = TEGRA186_SID_UFSHC, |
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.regs = { |
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.override = 0x488, |
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.security = 0x48c, |
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}, |
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}, { |
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.name = "nvdisplayr", |
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.sid = TEGRA186_SID_NVDISPLAY, |
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.regs = { |
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.override = 0x490, |
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.security = 0x494, |
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}, |
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}, { |
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.name = "bpmpr", |
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.sid = TEGRA186_SID_BPMP, |
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.regs = { |
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.override = 0x498, |
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.security = 0x49c, |
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}, |
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}, { |
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.name = "bpmpw", |
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.sid = TEGRA186_SID_BPMP, |
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.regs = { |
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.override = 0x4a0, |
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.security = 0x4a4, |
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}, |
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}, { |
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.name = "bpmpdmar", |
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.sid = TEGRA186_SID_BPMP, |
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.regs = { |
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.override = 0x4a8, |
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.security = 0x4ac, |
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}, |
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}, { |
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.name = "bpmpdmaw", |
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.sid = TEGRA186_SID_BPMP, |
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.regs = { |
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.override = 0x4b0, |
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.security = 0x4b4, |
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}, |
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}, { |
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.name = "aonr", |
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.sid = TEGRA186_SID_AON, |
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.regs = { |
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.override = 0x4b8, |
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.security = 0x4bc, |
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}, |
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}, { |
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.name = "aonw", |
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.sid = TEGRA186_SID_AON, |
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.regs = { |
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.override = 0x4c0, |
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.security = 0x4c4, |
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}, |
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}, { |
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.name = "aondmar", |
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.sid = TEGRA186_SID_AON, |
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.regs = { |
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.override = 0x4c8, |
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.security = 0x4cc, |
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}, |
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}, { |
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.name = "aondmaw", |
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.sid = TEGRA186_SID_AON, |
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.regs = { |
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.override = 0x4d0, |
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.security = 0x4d4, |
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}, |
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}, { |
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.name = "scer", |
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.sid = TEGRA186_SID_SCE, |
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.regs = { |
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.override = 0x4d8, |
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.security = 0x4dc, |
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}, |
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}, { |
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.name = "scew", |
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.sid = TEGRA186_SID_SCE, |
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.regs = { |
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.override = 0x4e0, |
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.security = 0x4e4, |
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}, |
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}, { |
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.name = "scedmar", |
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.sid = TEGRA186_SID_SCE, |
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.regs = { |
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.override = 0x4e8, |
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.security = 0x4ec, |
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}, |
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}, { |
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.name = "scedmaw", |
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.sid = TEGRA186_SID_SCE, |
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.regs = { |
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.override = 0x4f0, |
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.security = 0x4f4, |
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}, |
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}, { |
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.name = "apedmar", |
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.sid = TEGRA186_SID_APE, |
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.regs = { |
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.override = 0x4f8, |
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.security = 0x4fc, |
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}, |
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}, { |
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.name = "apedmaw", |
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.sid = TEGRA186_SID_APE, |
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.regs = { |
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.override = 0x500, |
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.security = 0x504, |
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}, |
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}, { |
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.name = "nvdisplayr1", |
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.sid = TEGRA186_SID_NVDISPLAY, |
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.regs = { |
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.override = 0x508, |
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.security = 0x50c, |
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}, |
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}, { |
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.name = "vicsrd1", |
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.sid = TEGRA186_SID_VIC, |
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.regs = { |
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.override = 0x510, |
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.security = 0x514, |
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}, |
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}, { |
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.name = "nvdecsrd1", |
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.sid = TEGRA186_SID_NVDEC, |
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.regs = { |
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.override = 0x518, |
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.security = 0x51c, |
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}, |
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}, |
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}; |
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|
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static const struct tegra186_mc_soc tegra186_mc_soc = { |
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.num_clients = ARRAY_SIZE(tegra186_mc_clients), |
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.clients = tegra186_mc_clients, |
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}; |
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#endif |
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|
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#if defined(CONFIG_ARCH_TEGRA_194_SOC) |
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static const struct tegra186_mc_client tegra194_mc_clients[] = { |
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{ |
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.name = "ptcr", |
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.sid = TEGRA194_SID_PASSTHROUGH, |
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.regs = { |
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.override = 0x000, |
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.security = 0x004, |
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}, |
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}, { |
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.name = "miu7r", |
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.sid = TEGRA194_SID_MIU, |
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.regs = { |
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.override = 0x008, |
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.security = 0x00c, |
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}, |
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}, { |
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.name = "miu7w", |
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.sid = TEGRA194_SID_MIU, |
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.regs = { |
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.override = 0x010, |
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.security = 0x014, |
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}, |
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}, { |
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.name = "hdar", |
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.sid = TEGRA194_SID_HDA, |
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.regs = { |
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.override = 0x0a8, |
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.security = 0x0ac, |
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}, |
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}, { |
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.name = "host1xdmar", |
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.sid = TEGRA194_SID_HOST1X, |
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.regs = { |
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.override = 0x0b0, |
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.security = 0x0b4, |
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}, |
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}, { |
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.name = "nvencsrd", |
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.sid = TEGRA194_SID_NVENC, |
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.regs = { |
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.override = 0x0e0, |
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.security = 0x0e4, |
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}, |
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}, { |
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.name = "satar", |
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.sid = TEGRA194_SID_SATA, |
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.regs = { |
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.override = 0x0f8, |
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.security = 0x0fc, |
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}, |
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}, { |
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.name = "mpcorer", |
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.sid = TEGRA194_SID_PASSTHROUGH, |
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.regs = { |
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.override = 0x138, |
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.security = 0x13c, |
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}, |
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}, { |
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.name = "nvencswr", |
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.sid = TEGRA194_SID_NVENC, |
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.regs = { |
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.override = 0x158, |
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.security = 0x15c, |
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}, |
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}, { |
|
.name = "hdaw", |
|
.sid = TEGRA194_SID_HDA, |
|
.regs = { |
|
.override = 0x1a8, |
|
.security = 0x1ac, |
|
}, |
|
}, { |
|
.name = "mpcorew", |
|
.sid = TEGRA194_SID_PASSTHROUGH, |
|
.regs = { |
|
.override = 0x1c8, |
|
.security = 0x1cc, |
|
}, |
|
}, { |
|
.name = "sataw", |
|
.sid = TEGRA194_SID_SATA, |
|
.regs = { |
|
.override = 0x1e8, |
|
.security = 0x1ec, |
|
}, |
|
}, { |
|
.name = "ispra", |
|
.sid = TEGRA194_SID_ISP, |
|
.regs = { |
|
.override = 0x220, |
|
.security = 0x224, |
|
}, |
|
}, { |
|
.name = "ispfalr", |
|
.sid = TEGRA194_SID_ISP_FALCON, |
|
.regs = { |
|
.override = 0x228, |
|
.security = 0x22c, |
|
}, |
|
}, { |
|
.name = "ispwa", |
|
.sid = TEGRA194_SID_ISP, |
|
.regs = { |
|
.override = 0x230, |
|
.security = 0x234, |
|
}, |
|
}, { |
|
.name = "ispwb", |
|
.sid = TEGRA194_SID_ISP, |
|
.regs = { |
|
.override = 0x238, |
|
.security = 0x23c, |
|
}, |
|
}, { |
|
.name = "xusb_hostr", |
|
.sid = TEGRA194_SID_XUSB_HOST, |
|
.regs = { |
|
.override = 0x250, |
|
.security = 0x254, |
|
}, |
|
}, { |
|
.name = "xusb_hostw", |
|
.sid = TEGRA194_SID_XUSB_HOST, |
|
.regs = { |
|
.override = 0x258, |
|
.security = 0x25c, |
|
}, |
|
}, { |
|
.name = "xusb_devr", |
|
.sid = TEGRA194_SID_XUSB_DEV, |
|
.regs = { |
|
.override = 0x260, |
|
.security = 0x264, |
|
}, |
|
}, { |
|
.name = "xusb_devw", |
|
.sid = TEGRA194_SID_XUSB_DEV, |
|
.regs = { |
|
.override = 0x268, |
|
.security = 0x26c, |
|
}, |
|
}, { |
|
.name = "sdmmcra", |
|
.sid = TEGRA194_SID_SDMMC1, |
|
.regs = { |
|
.override = 0x300, |
|
.security = 0x304, |
|
}, |
|
}, { |
|
.name = "sdmmcr", |
|
.sid = TEGRA194_SID_SDMMC3, |
|
.regs = { |
|
.override = 0x310, |
|
.security = 0x314, |
|
}, |
|
}, { |
|
.name = "sdmmcrab", |
|
.sid = TEGRA194_SID_SDMMC4, |
|
.regs = { |
|
.override = 0x318, |
|
.security = 0x31c, |
|
}, |
|
}, { |
|
.name = "sdmmcwa", |
|
.sid = TEGRA194_SID_SDMMC1, |
|
.regs = { |
|
.override = 0x320, |
|
.security = 0x324, |
|
}, |
|
}, { |
|
.name = "sdmmcw", |
|
.sid = TEGRA194_SID_SDMMC3, |
|
.regs = { |
|
.override = 0x330, |
|
.security = 0x334, |
|
}, |
|
}, { |
|
.name = "sdmmcwab", |
|
.sid = TEGRA194_SID_SDMMC4, |
|
.regs = { |
|
.override = 0x338, |
|
.security = 0x33c, |
|
}, |
|
}, { |
|
.name = "vicsrd", |
|
.sid = TEGRA194_SID_VIC, |
|
.regs = { |
|
.override = 0x360, |
|
.security = 0x364, |
|
}, |
|
}, { |
|
.name = "vicswr", |
|
.sid = TEGRA194_SID_VIC, |
|
.regs = { |
|
.override = 0x368, |
|
.security = 0x36c, |
|
}, |
|
}, { |
|
.name = "viw", |
|
.sid = TEGRA194_SID_VI, |
|
.regs = { |
|
.override = 0x390, |
|
.security = 0x394, |
|
}, |
|
}, { |
|
.name = "nvdecsrd", |
|
.sid = TEGRA194_SID_NVDEC, |
|
.regs = { |
|
.override = 0x3c0, |
|
.security = 0x3c4, |
|
}, |
|
}, { |
|
.name = "nvdecswr", |
|
.sid = TEGRA194_SID_NVDEC, |
|
.regs = { |
|
.override = 0x3c8, |
|
.security = 0x3cc, |
|
}, |
|
}, { |
|
.name = "aper", |
|
.sid = TEGRA194_SID_APE, |
|
.regs = { |
|
.override = 0x3c0, |
|
.security = 0x3c4, |
|
}, |
|
}, { |
|
.name = "apew", |
|
.sid = TEGRA194_SID_APE, |
|
.regs = { |
|
.override = 0x3d0, |
|
.security = 0x3d4, |
|
}, |
|
}, { |
|
.name = "nvjpgsrd", |
|
.sid = TEGRA194_SID_NVJPG, |
|
.regs = { |
|
.override = 0x3f0, |
|
.security = 0x3f4, |
|
}, |
|
}, { |
|
.name = "nvjpgswr", |
|
.sid = TEGRA194_SID_NVJPG, |
|
.regs = { |
|
.override = 0x3f0, |
|
.security = 0x3f4, |
|
}, |
|
}, { |
|
.name = "axiapr", |
|
.sid = TEGRA194_SID_PASSTHROUGH, |
|
.regs = { |
|
.override = 0x410, |
|
.security = 0x414, |
|
}, |
|
}, { |
|
.name = "axiapw", |
|
.sid = TEGRA194_SID_PASSTHROUGH, |
|
.regs = { |
|
.override = 0x418, |
|
.security = 0x41c, |
|
}, |
|
}, { |
|
.name = "etrr", |
|
.sid = TEGRA194_SID_ETR, |
|
.regs = { |
|
.override = 0x420, |
|
.security = 0x424, |
|
}, |
|
}, { |
|
.name = "etrw", |
|
.sid = TEGRA194_SID_ETR, |
|
.regs = { |
|
.override = 0x428, |
|
.security = 0x42c, |
|
}, |
|
}, { |
|
.name = "axisr", |
|
.sid = TEGRA194_SID_PASSTHROUGH, |
|
.regs = { |
|
.override = 0x460, |
|
.security = 0x464, |
|
}, |
|
}, { |
|
.name = "axisw", |
|
.sid = TEGRA194_SID_PASSTHROUGH, |
|
.regs = { |
|
.override = 0x468, |
|
.security = 0x46c, |
|
}, |
|
}, { |
|
.name = "eqosr", |
|
.sid = TEGRA194_SID_EQOS, |
|
.regs = { |
|
.override = 0x470, |
|
.security = 0x474, |
|
}, |
|
}, { |
|
.name = "eqosw", |
|
.sid = TEGRA194_SID_EQOS, |
|
.regs = { |
|
.override = 0x478, |
|
.security = 0x47c, |
|
}, |
|
}, { |
|
.name = "ufshcr", |
|
.sid = TEGRA194_SID_UFSHC, |
|
.regs = { |
|
.override = 0x480, |
|
.security = 0x484, |
|
}, |
|
}, { |
|
.name = "ufshcw", |
|
.sid = TEGRA194_SID_UFSHC, |
|
.regs = { |
|
.override = 0x488, |
|
.security = 0x48c, |
|
}, |
|
}, { |
|
.name = "nvdisplayr", |
|
.sid = TEGRA194_SID_NVDISPLAY, |
|
.regs = { |
|
.override = 0x490, |
|
.security = 0x494, |
|
}, |
|
}, { |
|
.name = "bpmpr", |
|
.sid = TEGRA194_SID_BPMP, |
|
.regs = { |
|
.override = 0x498, |
|
.security = 0x49c, |
|
}, |
|
}, { |
|
.name = "bpmpw", |
|
.sid = TEGRA194_SID_BPMP, |
|
.regs = { |
|
.override = 0x4a0, |
|
.security = 0x4a4, |
|
}, |
|
}, { |
|
.name = "bpmpdmar", |
|
.sid = TEGRA194_SID_BPMP, |
|
.regs = { |
|
.override = 0x4a8, |
|
.security = 0x4ac, |
|
}, |
|
}, { |
|
.name = "bpmpdmaw", |
|
.sid = TEGRA194_SID_BPMP, |
|
.regs = { |
|
.override = 0x4b0, |
|
.security = 0x4b4, |
|
}, |
|
}, { |
|
.name = "aonr", |
|
.sid = TEGRA194_SID_AON, |
|
.regs = { |
|
.override = 0x4b8, |
|
.security = 0x4bc, |
|
}, |
|
}, { |
|
.name = "aonw", |
|
.sid = TEGRA194_SID_AON, |
|
.regs = { |
|
.override = 0x4c0, |
|
.security = 0x4c4, |
|
}, |
|
}, { |
|
.name = "aondmar", |
|
.sid = TEGRA194_SID_AON, |
|
.regs = { |
|
.override = 0x4c8, |
|
.security = 0x4cc, |
|
}, |
|
}, { |
|
.name = "aondmaw", |
|
.sid = TEGRA194_SID_AON, |
|
.regs = { |
|
.override = 0x4d0, |
|
.security = 0x4d4, |
|
}, |
|
}, { |
|
.name = "scer", |
|
.sid = TEGRA194_SID_SCE, |
|
.regs = { |
|
.override = 0x4d8, |
|
.security = 0x4dc, |
|
}, |
|
}, { |
|
.name = "scew", |
|
.sid = TEGRA194_SID_SCE, |
|
.regs = { |
|
.override = 0x4e0, |
|
.security = 0x4e4, |
|
}, |
|
}, { |
|
.name = "scedmar", |
|
.sid = TEGRA194_SID_SCE, |
|
.regs = { |
|
.override = 0x4e8, |
|
.security = 0x4ec, |
|
}, |
|
}, { |
|
.name = "scedmaw", |
|
.sid = TEGRA194_SID_SCE, |
|
.regs = { |
|
.override = 0x4f0, |
|
.security = 0x4f4, |
|
}, |
|
}, { |
|
.name = "apedmar", |
|
.sid = TEGRA194_SID_APE, |
|
.regs = { |
|
.override = 0x4f8, |
|
.security = 0x4fc, |
|
}, |
|
}, { |
|
.name = "apedmaw", |
|
.sid = TEGRA194_SID_APE, |
|
.regs = { |
|
.override = 0x500, |
|
.security = 0x504, |
|
}, |
|
}, { |
|
.name = "nvdisplayr1", |
|
.sid = TEGRA194_SID_NVDISPLAY, |
|
.regs = { |
|
.override = 0x508, |
|
.security = 0x50c, |
|
}, |
|
}, { |
|
.name = "vicsrd1", |
|
.sid = TEGRA194_SID_VIC, |
|
.regs = { |
|
.override = 0x510, |
|
.security = 0x514, |
|
}, |
|
}, { |
|
.name = "nvdecsrd1", |
|
.sid = TEGRA194_SID_NVDEC, |
|
.regs = { |
|
.override = 0x518, |
|
.security = 0x51c, |
|
}, |
|
}, { |
|
.name = "miu0r", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x530, |
|
.security = 0x534, |
|
}, |
|
}, { |
|
.name = "miu0w", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x538, |
|
.security = 0x53c, |
|
}, |
|
}, { |
|
.name = "miu1r", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x540, |
|
.security = 0x544, |
|
}, |
|
}, { |
|
.name = "miu1w", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x548, |
|
.security = 0x54c, |
|
}, |
|
}, { |
|
.name = "miu2r", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x570, |
|
.security = 0x574, |
|
}, |
|
}, { |
|
.name = "miu2w", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x578, |
|
.security = 0x57c, |
|
}, |
|
}, { |
|
.name = "miu3r", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x580, |
|
.security = 0x584, |
|
}, |
|
}, { |
|
.name = "miu3w", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x588, |
|
.security = 0x58c, |
|
}, |
|
}, { |
|
.name = "miu4r", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x590, |
|
.security = 0x594, |
|
}, |
|
}, { |
|
.name = "miu4w", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x598, |
|
.security = 0x59c, |
|
}, |
|
}, { |
|
.name = "dpmur", |
|
.sid = TEGRA194_SID_PASSTHROUGH, |
|
.regs = { |
|
.override = 0x598, |
|
.security = 0x59c, |
|
}, |
|
}, { |
|
.name = "vifalr", |
|
.sid = TEGRA194_SID_VI_FALCON, |
|
.regs = { |
|
.override = 0x5e0, |
|
.security = 0x5e4, |
|
}, |
|
}, { |
|
.name = "vifalw", |
|
.sid = TEGRA194_SID_VI_FALCON, |
|
.regs = { |
|
.override = 0x5e8, |
|
.security = 0x5ec, |
|
}, |
|
}, { |
|
.name = "dla0rda", |
|
.sid = TEGRA194_SID_NVDLA0, |
|
.regs = { |
|
.override = 0x5f0, |
|
.security = 0x5f4, |
|
}, |
|
}, { |
|
.name = "dla0falrdb", |
|
.sid = TEGRA194_SID_NVDLA0, |
|
.regs = { |
|
.override = 0x5f8, |
|
.security = 0x5fc, |
|
}, |
|
}, { |
|
.name = "dla0wra", |
|
.sid = TEGRA194_SID_NVDLA0, |
|
.regs = { |
|
.override = 0x600, |
|
.security = 0x604, |
|
}, |
|
}, { |
|
.name = "dla0falwrb", |
|
.sid = TEGRA194_SID_NVDLA0, |
|
.regs = { |
|
.override = 0x608, |
|
.security = 0x60c, |
|
}, |
|
}, { |
|
.name = "dla1rda", |
|
.sid = TEGRA194_SID_NVDLA1, |
|
.regs = { |
|
.override = 0x610, |
|
.security = 0x614, |
|
}, |
|
}, { |
|
.name = "dla1falrdb", |
|
.sid = TEGRA194_SID_NVDLA1, |
|
.regs = { |
|
.override = 0x618, |
|
.security = 0x61c, |
|
}, |
|
}, { |
|
.name = "dla1wra", |
|
.sid = TEGRA194_SID_NVDLA1, |
|
.regs = { |
|
.override = 0x620, |
|
.security = 0x624, |
|
}, |
|
}, { |
|
.name = "dla1falwrb", |
|
.sid = TEGRA194_SID_NVDLA1, |
|
.regs = { |
|
.override = 0x628, |
|
.security = 0x62c, |
|
}, |
|
}, { |
|
.name = "pva0rda", |
|
.sid = TEGRA194_SID_PVA0, |
|
.regs = { |
|
.override = 0x630, |
|
.security = 0x634, |
|
}, |
|
}, { |
|
.name = "pva0rdb", |
|
.sid = TEGRA194_SID_PVA0, |
|
.regs = { |
|
.override = 0x638, |
|
.security = 0x63c, |
|
}, |
|
}, { |
|
.name = "pva0rdc", |
|
.sid = TEGRA194_SID_PVA0, |
|
.regs = { |
|
.override = 0x640, |
|
.security = 0x644, |
|
}, |
|
}, { |
|
.name = "pva0wra", |
|
.sid = TEGRA194_SID_PVA0, |
|
.regs = { |
|
.override = 0x648, |
|
.security = 0x64c, |
|
}, |
|
}, { |
|
.name = "pva0wrb", |
|
.sid = TEGRA194_SID_PVA0, |
|
.regs = { |
|
.override = 0x650, |
|
.security = 0x654, |
|
}, |
|
}, { |
|
.name = "pva0wrc", |
|
.sid = TEGRA194_SID_PVA0, |
|
.regs = { |
|
.override = 0x658, |
|
.security = 0x65c, |
|
}, |
|
}, { |
|
.name = "pva1rda", |
|
.sid = TEGRA194_SID_PVA1, |
|
.regs = { |
|
.override = 0x660, |
|
.security = 0x664, |
|
}, |
|
}, { |
|
.name = "pva1rdb", |
|
.sid = TEGRA194_SID_PVA1, |
|
.regs = { |
|
.override = 0x668, |
|
.security = 0x66c, |
|
}, |
|
}, { |
|
.name = "pva1rdc", |
|
.sid = TEGRA194_SID_PVA1, |
|
.regs = { |
|
.override = 0x670, |
|
.security = 0x674, |
|
}, |
|
}, { |
|
.name = "pva1wra", |
|
.sid = TEGRA194_SID_PVA1, |
|
.regs = { |
|
.override = 0x678, |
|
.security = 0x67c, |
|
}, |
|
}, { |
|
.name = "pva1wrb", |
|
.sid = TEGRA194_SID_PVA1, |
|
.regs = { |
|
.override = 0x680, |
|
.security = 0x684, |
|
}, |
|
}, { |
|
.name = "pva1wrc", |
|
.sid = TEGRA194_SID_PVA1, |
|
.regs = { |
|
.override = 0x688, |
|
.security = 0x68c, |
|
}, |
|
}, { |
|
.name = "rcer", |
|
.sid = TEGRA194_SID_RCE, |
|
.regs = { |
|
.override = 0x690, |
|
.security = 0x694, |
|
}, |
|
}, { |
|
.name = "rcew", |
|
.sid = TEGRA194_SID_RCE, |
|
.regs = { |
|
.override = 0x698, |
|
.security = 0x69c, |
|
}, |
|
}, { |
|
.name = "rcedmar", |
|
.sid = TEGRA194_SID_RCE, |
|
.regs = { |
|
.override = 0x6a0, |
|
.security = 0x6a4, |
|
}, |
|
}, { |
|
.name = "rcedmaw", |
|
.sid = TEGRA194_SID_RCE, |
|
.regs = { |
|
.override = 0x6a8, |
|
.security = 0x6ac, |
|
}, |
|
}, { |
|
.name = "nvenc1srd", |
|
.sid = TEGRA194_SID_NVENC1, |
|
.regs = { |
|
.override = 0x6b0, |
|
.security = 0x6b4, |
|
}, |
|
}, { |
|
.name = "nvenc1swr", |
|
.sid = TEGRA194_SID_NVENC1, |
|
.regs = { |
|
.override = 0x6b8, |
|
.security = 0x6bc, |
|
}, |
|
}, { |
|
.name = "pcie0r", |
|
.sid = TEGRA194_SID_PCIE0, |
|
.regs = { |
|
.override = 0x6c0, |
|
.security = 0x6c4, |
|
}, |
|
}, { |
|
.name = "pcie0w", |
|
.sid = TEGRA194_SID_PCIE0, |
|
.regs = { |
|
.override = 0x6c8, |
|
.security = 0x6cc, |
|
}, |
|
}, { |
|
.name = "pcie1r", |
|
.sid = TEGRA194_SID_PCIE1, |
|
.regs = { |
|
.override = 0x6d0, |
|
.security = 0x6d4, |
|
}, |
|
}, { |
|
.name = "pcie1w", |
|
.sid = TEGRA194_SID_PCIE1, |
|
.regs = { |
|
.override = 0x6d8, |
|
.security = 0x6dc, |
|
}, |
|
}, { |
|
.name = "pcie2ar", |
|
.sid = TEGRA194_SID_PCIE2, |
|
.regs = { |
|
.override = 0x6e0, |
|
.security = 0x6e4, |
|
}, |
|
}, { |
|
.name = "pcie2aw", |
|
.sid = TEGRA194_SID_PCIE2, |
|
.regs = { |
|
.override = 0x6e8, |
|
.security = 0x6ec, |
|
}, |
|
}, { |
|
.name = "pcie3r", |
|
.sid = TEGRA194_SID_PCIE3, |
|
.regs = { |
|
.override = 0x6f0, |
|
.security = 0x6f4, |
|
}, |
|
}, { |
|
.name = "pcie3w", |
|
.sid = TEGRA194_SID_PCIE3, |
|
.regs = { |
|
.override = 0x6f8, |
|
.security = 0x6fc, |
|
}, |
|
}, { |
|
.name = "pcie4r", |
|
.sid = TEGRA194_SID_PCIE4, |
|
.regs = { |
|
.override = 0x700, |
|
.security = 0x704, |
|
}, |
|
}, { |
|
.name = "pcie4w", |
|
.sid = TEGRA194_SID_PCIE4, |
|
.regs = { |
|
.override = 0x708, |
|
.security = 0x70c, |
|
}, |
|
}, { |
|
.name = "pcie5r", |
|
.sid = TEGRA194_SID_PCIE5, |
|
.regs = { |
|
.override = 0x710, |
|
.security = 0x714, |
|
}, |
|
}, { |
|
.name = "pcie5w", |
|
.sid = TEGRA194_SID_PCIE5, |
|
.regs = { |
|
.override = 0x718, |
|
.security = 0x71c, |
|
}, |
|
}, { |
|
.name = "ispfalw", |
|
.sid = TEGRA194_SID_ISP_FALCON, |
|
.regs = { |
|
.override = 0x720, |
|
.security = 0x724, |
|
}, |
|
}, { |
|
.name = "dla0rda1", |
|
.sid = TEGRA194_SID_NVDLA0, |
|
.regs = { |
|
.override = 0x748, |
|
.security = 0x74c, |
|
}, |
|
}, { |
|
.name = "dla1rda1", |
|
.sid = TEGRA194_SID_NVDLA1, |
|
.regs = { |
|
.override = 0x750, |
|
.security = 0x754, |
|
}, |
|
}, { |
|
.name = "pva0rda1", |
|
.sid = TEGRA194_SID_PVA0, |
|
.regs = { |
|
.override = 0x758, |
|
.security = 0x75c, |
|
}, |
|
}, { |
|
.name = "pva0rdb1", |
|
.sid = TEGRA194_SID_PVA0, |
|
.regs = { |
|
.override = 0x760, |
|
.security = 0x764, |
|
}, |
|
}, { |
|
.name = "pva1rda1", |
|
.sid = TEGRA194_SID_PVA1, |
|
.regs = { |
|
.override = 0x768, |
|
.security = 0x76c, |
|
}, |
|
}, { |
|
.name = "pva1rdb1", |
|
.sid = TEGRA194_SID_PVA1, |
|
.regs = { |
|
.override = 0x770, |
|
.security = 0x774, |
|
}, |
|
}, { |
|
.name = "pcie5r1", |
|
.sid = TEGRA194_SID_PCIE5, |
|
.regs = { |
|
.override = 0x778, |
|
.security = 0x77c, |
|
}, |
|
}, { |
|
.name = "nvencsrd1", |
|
.sid = TEGRA194_SID_NVENC, |
|
.regs = { |
|
.override = 0x780, |
|
.security = 0x784, |
|
}, |
|
}, { |
|
.name = "nvenc1srd1", |
|
.sid = TEGRA194_SID_NVENC1, |
|
.regs = { |
|
.override = 0x788, |
|
.security = 0x78c, |
|
}, |
|
}, { |
|
.name = "ispra1", |
|
.sid = TEGRA194_SID_ISP, |
|
.regs = { |
|
.override = 0x790, |
|
.security = 0x794, |
|
}, |
|
}, { |
|
.name = "pcie0r1", |
|
.sid = TEGRA194_SID_PCIE0, |
|
.regs = { |
|
.override = 0x798, |
|
.security = 0x79c, |
|
}, |
|
}, { |
|
.name = "nvdec1srd", |
|
.sid = TEGRA194_SID_NVDEC1, |
|
.regs = { |
|
.override = 0x7c8, |
|
.security = 0x7cc, |
|
}, |
|
}, { |
|
.name = "nvdec1srd1", |
|
.sid = TEGRA194_SID_NVDEC1, |
|
.regs = { |
|
.override = 0x7d0, |
|
.security = 0x7d4, |
|
}, |
|
}, { |
|
.name = "nvdec1swr", |
|
.sid = TEGRA194_SID_NVDEC1, |
|
.regs = { |
|
.override = 0x7d8, |
|
.security = 0x7dc, |
|
}, |
|
}, { |
|
.name = "miu5r", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x7e0, |
|
.security = 0x7e4, |
|
}, |
|
}, { |
|
.name = "miu5w", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x7e8, |
|
.security = 0x7ec, |
|
}, |
|
}, { |
|
.name = "miu6r", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x7f0, |
|
.security = 0x7f4, |
|
}, |
|
}, { |
|
.name = "miu6w", |
|
.sid = TEGRA194_SID_MIU, |
|
.regs = { |
|
.override = 0x7f8, |
|
.security = 0x7fc, |
|
}, |
|
}, |
|
}; |
|
|
|
static const struct tegra186_mc_soc tegra194_mc_soc = { |
|
.num_clients = ARRAY_SIZE(tegra194_mc_clients), |
|
.clients = tegra194_mc_clients, |
|
}; |
|
#endif |
|
|
|
static int tegra186_mc_probe(struct platform_device *pdev) |
|
{ |
|
struct tegra186_mc *mc; |
|
struct resource *res; |
|
int err; |
|
|
|
mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); |
|
if (!mc) |
|
return -ENOMEM; |
|
|
|
mc->soc = of_device_get_match_data(&pdev->dev); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
mc->regs = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(mc->regs)) |
|
return PTR_ERR(mc->regs); |
|
|
|
mc->dev = &pdev->dev; |
|
|
|
err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); |
|
if (err < 0) |
|
return err; |
|
|
|
platform_set_drvdata(pdev, mc); |
|
tegra186_mc_program_sid(mc); |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra186_mc_remove(struct platform_device *pdev) |
|
{ |
|
struct tegra186_mc *mc = platform_get_drvdata(pdev); |
|
|
|
of_platform_depopulate(mc->dev); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id tegra186_mc_of_match[] = { |
|
#if defined(CONFIG_ARCH_TEGRA_186_SOC) |
|
{ .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, |
|
#endif |
|
#if defined(CONFIG_ARCH_TEGRA_194_SOC) |
|
{ .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, |
|
#endif |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, tegra186_mc_of_match); |
|
|
|
static int __maybe_unused tegra186_mc_suspend(struct device *dev) |
|
{ |
|
return 0; |
|
} |
|
|
|
static int __maybe_unused tegra186_mc_resume(struct device *dev) |
|
{ |
|
struct tegra186_mc *mc = dev_get_drvdata(dev); |
|
|
|
tegra186_mc_program_sid(mc); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops tegra186_mc_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(tegra186_mc_suspend, tegra186_mc_resume) |
|
}; |
|
|
|
static struct platform_driver tegra186_mc_driver = { |
|
.driver = { |
|
.name = "tegra186-mc", |
|
.of_match_table = tegra186_mc_of_match, |
|
.pm = &tegra186_mc_pm_ops, |
|
.suppress_bind_attrs = true, |
|
}, |
|
.probe = tegra186_mc_probe, |
|
.remove = tegra186_mc_remove, |
|
}; |
|
module_platform_driver(tegra186_mc_driver); |
|
|
|
MODULE_AUTHOR("Thierry Reding <[email protected]>"); |
|
MODULE_DESCRIPTION("NVIDIA Tegra186 Memory Controller driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|