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406 lines
10 KiB
406 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Hisilicon HiP04 INTC |
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* |
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* Copyright (C) 2002-2014 ARM Limited. |
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* Copyright (c) 2013-2014 Hisilicon Ltd. |
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* Copyright (c) 2013-2014 Linaro Ltd. |
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* |
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* Interrupt architecture for the HIP04 INTC: |
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* |
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* o There is one Interrupt Distributor, which receives interrupts |
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* from system devices and sends them to the Interrupt Controllers. |
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* |
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* o There is one CPU Interface per CPU, which sends interrupts sent |
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* by the Distributor, and interrupts generated locally, to the |
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* associated CPU. The base address of the CPU interface is usually |
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* aliased so that the same address points to different chips depending |
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* on the CPU it is accessed from. |
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* |
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* Note that IRQs 0-31 are special - they are local to each CPU. |
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* As such, the enable set/clear, pending set/clear and active bit |
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* registers are banked per-cpu for these sources. |
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*/ |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/err.h> |
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#include <linux/module.h> |
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#include <linux/list.h> |
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#include <linux/smp.h> |
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#include <linux/cpu.h> |
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#include <linux/cpu_pm.h> |
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#include <linux/cpumask.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/interrupt.h> |
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#include <linux/slab.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/arm-gic.h> |
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#include <asm/irq.h> |
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#include <asm/exception.h> |
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#include <asm/smp_plat.h> |
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#include "irq-gic-common.h" |
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#define HIP04_MAX_IRQS 510 |
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struct hip04_irq_data { |
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void __iomem *dist_base; |
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void __iomem *cpu_base; |
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struct irq_domain *domain; |
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unsigned int nr_irqs; |
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}; |
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static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
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/* |
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* The GIC mapping of CPU interfaces does not necessarily match |
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* the logical CPU numbering. Let's use a mapping as returned |
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* by the GIC itself. |
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*/ |
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#define NR_HIP04_CPU_IF 16 |
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static u16 hip04_cpu_map[NR_HIP04_CPU_IF] __read_mostly; |
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static struct hip04_irq_data hip04_data __read_mostly; |
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static inline void __iomem *hip04_dist_base(struct irq_data *d) |
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{ |
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struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d); |
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return hip04_data->dist_base; |
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} |
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static inline void __iomem *hip04_cpu_base(struct irq_data *d) |
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{ |
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struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d); |
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return hip04_data->cpu_base; |
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} |
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static inline unsigned int hip04_irq(struct irq_data *d) |
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{ |
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return d->hwirq; |
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} |
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/* |
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* Routines to acknowledge, disable and enable interrupts |
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*/ |
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static void hip04_mask_irq(struct irq_data *d) |
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{ |
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u32 mask = 1 << (hip04_irq(d) % 32); |
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raw_spin_lock(&irq_controller_lock); |
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writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR + |
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(hip04_irq(d) / 32) * 4); |
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raw_spin_unlock(&irq_controller_lock); |
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} |
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static void hip04_unmask_irq(struct irq_data *d) |
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{ |
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u32 mask = 1 << (hip04_irq(d) % 32); |
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raw_spin_lock(&irq_controller_lock); |
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writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + |
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(hip04_irq(d) / 32) * 4); |
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raw_spin_unlock(&irq_controller_lock); |
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} |
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static void hip04_eoi_irq(struct irq_data *d) |
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{ |
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writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI); |
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} |
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static int hip04_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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void __iomem *base = hip04_dist_base(d); |
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unsigned int irq = hip04_irq(d); |
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int ret; |
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/* Interrupt configuration for SGIs can't be changed */ |
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if (irq < 16) |
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return -EINVAL; |
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/* SPIs have restrictions on the supported types */ |
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if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && |
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type != IRQ_TYPE_EDGE_RISING) |
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return -EINVAL; |
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raw_spin_lock(&irq_controller_lock); |
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ret = gic_configure_irq(irq, type, base + GIC_DIST_CONFIG, NULL); |
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if (ret && irq < 32) { |
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/* Misconfigured PPIs are usually not fatal */ |
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pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16); |
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ret = 0; |
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} |
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raw_spin_unlock(&irq_controller_lock); |
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return ret; |
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} |
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#ifdef CONFIG_SMP |
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static int hip04_irq_set_affinity(struct irq_data *d, |
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const struct cpumask *mask_val, |
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bool force) |
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{ |
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void __iomem *reg; |
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unsigned int cpu, shift = (hip04_irq(d) % 2) * 16; |
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u32 val, mask, bit; |
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if (!force) |
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cpu = cpumask_any_and(mask_val, cpu_online_mask); |
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else |
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cpu = cpumask_first(mask_val); |
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if (cpu >= NR_HIP04_CPU_IF || cpu >= nr_cpu_ids) |
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return -EINVAL; |
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raw_spin_lock(&irq_controller_lock); |
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reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3); |
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mask = 0xffff << shift; |
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bit = hip04_cpu_map[cpu] << shift; |
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val = readl_relaxed(reg) & ~mask; |
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writel_relaxed(val | bit, reg); |
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raw_spin_unlock(&irq_controller_lock); |
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irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
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return IRQ_SET_MASK_OK; |
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} |
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static void hip04_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) |
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{ |
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int cpu; |
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unsigned long flags, map = 0; |
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raw_spin_lock_irqsave(&irq_controller_lock, flags); |
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/* Convert our logical CPU mask into a physical one. */ |
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for_each_cpu(cpu, mask) |
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map |= hip04_cpu_map[cpu]; |
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/* |
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* Ensure that stores to Normal memory are visible to the |
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* other CPUs before they observe us issuing the IPI. |
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*/ |
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dmb(ishst); |
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/* this always happens on GIC0 */ |
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writel_relaxed(map << 8 | d->hwirq, hip04_data.dist_base + GIC_DIST_SOFTINT); |
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raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
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} |
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#endif |
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static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs) |
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{ |
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u32 irqstat, irqnr; |
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void __iomem *cpu_base = hip04_data.cpu_base; |
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do { |
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irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); |
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irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
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if (irqnr <= HIP04_MAX_IRQS) |
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handle_domain_irq(hip04_data.domain, irqnr, regs); |
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} while (irqnr > HIP04_MAX_IRQS); |
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} |
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static struct irq_chip hip04_irq_chip = { |
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.name = "HIP04 INTC", |
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.irq_mask = hip04_mask_irq, |
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.irq_unmask = hip04_unmask_irq, |
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.irq_eoi = hip04_eoi_irq, |
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.irq_set_type = hip04_irq_set_type, |
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#ifdef CONFIG_SMP |
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.irq_set_affinity = hip04_irq_set_affinity, |
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.ipi_send_mask = hip04_ipi_send_mask, |
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#endif |
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.flags = IRQCHIP_SET_TYPE_MASKED | |
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IRQCHIP_SKIP_SET_WAKE | |
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IRQCHIP_MASK_ON_SUSPEND, |
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}; |
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static u16 hip04_get_cpumask(struct hip04_irq_data *intc) |
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{ |
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void __iomem *base = intc->dist_base; |
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u32 mask, i; |
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for (i = mask = 0; i < 32; i += 2) { |
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mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2); |
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mask |= mask >> 16; |
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if (mask) |
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break; |
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} |
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if (!mask) |
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pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
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return mask; |
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} |
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static void __init hip04_irq_dist_init(struct hip04_irq_data *intc) |
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{ |
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unsigned int i; |
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u32 cpumask; |
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unsigned int nr_irqs = intc->nr_irqs; |
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void __iomem *base = intc->dist_base; |
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writel_relaxed(0, base + GIC_DIST_CTRL); |
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/* |
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* Set all global interrupts to this CPU only. |
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*/ |
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cpumask = hip04_get_cpumask(intc); |
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cpumask |= cpumask << 16; |
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for (i = 32; i < nr_irqs; i += 2) |
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writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); |
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gic_dist_config(base, nr_irqs, NULL); |
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writel_relaxed(1, base + GIC_DIST_CTRL); |
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} |
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static void hip04_irq_cpu_init(struct hip04_irq_data *intc) |
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{ |
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void __iomem *dist_base = intc->dist_base; |
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void __iomem *base = intc->cpu_base; |
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unsigned int cpu_mask, cpu = smp_processor_id(); |
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int i; |
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/* |
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* Get what the GIC says our CPU mask is. |
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*/ |
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BUG_ON(cpu >= NR_HIP04_CPU_IF); |
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cpu_mask = hip04_get_cpumask(intc); |
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hip04_cpu_map[cpu] = cpu_mask; |
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/* |
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* Clear our mask from the other map entries in case they're |
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* still undefined. |
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*/ |
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for (i = 0; i < NR_HIP04_CPU_IF; i++) |
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if (i != cpu) |
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hip04_cpu_map[i] &= ~cpu_mask; |
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gic_cpu_config(dist_base, 32, NULL); |
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writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); |
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writel_relaxed(1, base + GIC_CPU_CTRL); |
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} |
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static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq, |
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irq_hw_number_t hw) |
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{ |
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if (hw < 32) { |
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irq_set_percpu_devid(irq); |
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irq_set_chip_and_handler(irq, &hip04_irq_chip, |
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handle_percpu_devid_irq); |
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} else { |
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irq_set_chip_and_handler(irq, &hip04_irq_chip, |
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handle_fasteoi_irq); |
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irq_set_probe(irq); |
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irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); |
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} |
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irq_set_chip_data(irq, d->host_data); |
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return 0; |
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} |
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static int hip04_irq_domain_xlate(struct irq_domain *d, |
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struct device_node *controller, |
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const u32 *intspec, unsigned int intsize, |
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unsigned long *out_hwirq, |
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unsigned int *out_type) |
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{ |
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if (irq_domain_get_of_node(d) != controller) |
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return -EINVAL; |
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if (intsize == 1 && intspec[0] < 16) { |
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*out_hwirq = intspec[0]; |
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*out_type = IRQ_TYPE_EDGE_RISING; |
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return 0; |
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} |
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if (intsize < 3) |
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return -EINVAL; |
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/* Get the interrupt number and add 16 to skip over SGIs */ |
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*out_hwirq = intspec[1] + 16; |
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/* For SPIs, we need to add 16 more to get the irq ID number */ |
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if (!intspec[0]) |
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*out_hwirq += 16; |
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*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
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return 0; |
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} |
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static int hip04_irq_starting_cpu(unsigned int cpu) |
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{ |
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hip04_irq_cpu_init(&hip04_data); |
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return 0; |
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} |
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static const struct irq_domain_ops hip04_irq_domain_ops = { |
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.map = hip04_irq_domain_map, |
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.xlate = hip04_irq_domain_xlate, |
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}; |
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static int __init |
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hip04_of_init(struct device_node *node, struct device_node *parent) |
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{ |
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int nr_irqs, irq_base, i; |
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if (WARN_ON(!node)) |
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return -ENODEV; |
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hip04_data.dist_base = of_iomap(node, 0); |
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WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n"); |
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hip04_data.cpu_base = of_iomap(node, 1); |
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WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n"); |
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/* |
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* Initialize the CPU interface map to all CPUs. |
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* It will be refined as each CPU probes its ID. |
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*/ |
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for (i = 0; i < NR_HIP04_CPU_IF; i++) |
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hip04_cpu_map[i] = 0xffff; |
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/* |
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* Find out how many interrupts are supported. |
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* The HIP04 INTC only supports up to 510 interrupt sources. |
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*/ |
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nr_irqs = readl_relaxed(hip04_data.dist_base + GIC_DIST_CTR) & 0x1f; |
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nr_irqs = (nr_irqs + 1) * 32; |
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if (nr_irqs > HIP04_MAX_IRQS) |
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nr_irqs = HIP04_MAX_IRQS; |
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hip04_data.nr_irqs = nr_irqs; |
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irq_base = irq_alloc_descs(-1, 0, nr_irqs, numa_node_id()); |
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if (irq_base < 0) { |
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pr_err("failed to allocate IRQ numbers\n"); |
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return -EINVAL; |
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} |
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hip04_data.domain = irq_domain_add_legacy(node, nr_irqs, irq_base, |
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0, |
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&hip04_irq_domain_ops, |
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&hip04_data); |
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if (WARN_ON(!hip04_data.domain)) |
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return -EINVAL; |
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#ifdef CONFIG_SMP |
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set_smp_ipi_range(irq_base, 16); |
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#endif |
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set_handle_irq(hip04_handle_irq); |
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hip04_irq_dist_init(&hip04_data); |
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cpuhp_setup_state(CPUHP_AP_IRQ_HIP04_STARTING, "irqchip/hip04:starting", |
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hip04_irq_starting_cpu, NULL); |
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return 0; |
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} |
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IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init);
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