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640 lines
14 KiB
640 lines
14 KiB
/* QLogic qedr NIC Driver |
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* Copyright (c) 2015-2016 QLogic Corporation |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenIB.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and /or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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#ifndef __QEDR_H__ |
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#define __QEDR_H__ |
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|
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#include <linux/pci.h> |
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#include <linux/xarray.h> |
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#include <rdma/ib_addr.h> |
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#include <linux/qed/qed_if.h> |
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#include <linux/qed/qed_chain.h> |
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#include <linux/qed/qed_rdma_if.h> |
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#include <linux/qed/qede_rdma.h> |
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#include <linux/qed/roce_common.h> |
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#include <linux/completion.h> |
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#include "qedr_hsi_rdma.h" |
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|
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#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA" |
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#define DP_NAME(_dev) dev_name(&(_dev)->ibdev.dev) |
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#define IS_IWARP(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_IWARP) |
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#define IS_ROCE(_dev) ((_dev)->rdma_type == QED_RDMA_TYPE_ROCE) |
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#define DP_DEBUG(dev, module, fmt, ...) \ |
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pr_debug("(%s) " module ": " fmt, \ |
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DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__) |
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#define QEDR_MSG_INIT "INIT" |
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#define QEDR_MSG_MISC "MISC" |
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#define QEDR_MSG_CQ " CQ" |
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#define QEDR_MSG_MR " MR" |
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#define QEDR_MSG_RQ " RQ" |
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#define QEDR_MSG_SQ " SQ" |
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#define QEDR_MSG_QP " QP" |
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#define QEDR_MSG_SRQ " SRQ" |
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#define QEDR_MSG_GSI " GSI" |
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#define QEDR_MSG_IWARP " IW" |
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#define QEDR_CQ_MAGIC_NUMBER (0x11223344) |
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#define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE) |
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#define FW_PAGE_SHIFT (12) |
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struct qedr_dev; |
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struct qedr_cnq { |
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struct qedr_dev *dev; |
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struct qed_chain pbl; |
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struct qed_sb_info *sb; |
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char name[32]; |
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u64 n_comp; |
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__le16 *hw_cons_ptr; |
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u8 index; |
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}; |
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#define QEDR_MAX_SGID 128 |
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struct qedr_device_attr { |
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u32 vendor_id; |
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u32 vendor_part_id; |
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u32 hw_ver; |
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u64 fw_ver; |
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u64 node_guid; |
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u64 sys_image_guid; |
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u8 max_cnq; |
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u8 max_sge; |
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u16 max_inline; |
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u32 max_sqe; |
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u32 max_rqe; |
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u8 max_qp_resp_rd_atomic_resc; |
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u8 max_qp_req_rd_atomic_resc; |
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u64 max_dev_resp_rd_atomic_resc; |
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u32 max_cq; |
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u32 max_qp; |
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u32 max_mr; |
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u64 max_mr_size; |
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u32 max_cqe; |
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u32 max_mw; |
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u32 max_mr_mw_fmr_pbl; |
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u64 max_mr_mw_fmr_size; |
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u32 max_pd; |
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u32 max_ah; |
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u8 max_pkey; |
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u32 max_srq; |
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u32 max_srq_wr; |
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u8 max_srq_sge; |
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u8 max_stats_queues; |
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u32 dev_caps; |
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u64 page_size_caps; |
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u8 dev_ack_delay; |
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u32 reserved_lkey; |
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u32 bad_pkey_counter; |
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struct qed_rdma_events events; |
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}; |
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#define QEDR_ENET_STATE_BIT (0) |
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struct qedr_dev { |
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struct ib_device ibdev; |
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struct qed_dev *cdev; |
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struct pci_dev *pdev; |
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struct net_device *ndev; |
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enum ib_atomic_cap atomic_cap; |
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void *rdma_ctx; |
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struct qedr_device_attr attr; |
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const struct qed_rdma_ops *ops; |
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struct qed_int_info int_info; |
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struct qed_sb_info *sb_array; |
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struct qedr_cnq *cnq_array; |
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int num_cnq; |
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int sb_start; |
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void __iomem *db_addr; |
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u64 db_phys_addr; |
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u32 db_size; |
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u16 dpi; |
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union ib_gid *sgid_tbl; |
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/* Lock for sgid table */ |
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spinlock_t sgid_lock; |
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u64 guid; |
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u32 dp_module; |
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u8 dp_level; |
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u8 num_hwfns; |
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#define QEDR_IS_CMT(dev) ((dev)->num_hwfns > 1) |
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u8 affin_hwfn_idx; |
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u8 gsi_ll2_handle; |
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uint wq_multiplier; |
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u8 gsi_ll2_mac_address[ETH_ALEN]; |
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int gsi_qp_created; |
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struct qedr_cq *gsi_sqcq; |
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struct qedr_cq *gsi_rqcq; |
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struct qedr_qp *gsi_qp; |
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enum qed_rdma_type rdma_type; |
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struct xarray qps; |
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struct xarray srqs; |
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struct workqueue_struct *iwarp_wq; |
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u16 iwarp_max_mtu; |
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unsigned long enet_state; |
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u8 user_dpm_enabled; |
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}; |
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#define QEDR_MAX_SQ_PBL (0x8000) |
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#define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) |
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#define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) |
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#define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ |
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QEDR_SQE_ELEMENT_SIZE) |
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#define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ |
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QEDR_SQE_ELEMENT_SIZE) |
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#define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\ |
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(RDMA_RING_PAGE_SIZE) / \ |
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(QEDR_SQE_ELEMENT_SIZE) /\ |
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(QEDR_MAX_SQE_ELEMENTS_PER_SQE)) |
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/* RQ */ |
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#define QEDR_MAX_RQ_PBL (0x2000) |
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#define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) |
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#define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) |
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#define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) |
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#define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ |
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QEDR_RQE_ELEMENT_SIZE) |
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#define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\ |
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(RDMA_RING_PAGE_SIZE) / \ |
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(QEDR_RQE_ELEMENT_SIZE) /\ |
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(QEDR_MAX_RQE_ELEMENTS_PER_RQE)) |
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#define QEDR_CQE_SIZE (sizeof(union rdma_cqe)) |
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#define QEDR_MAX_CQE_PBL_SIZE (512 * 1024) |
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#define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \ |
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sizeof(u64)) - 1) |
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#define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \ |
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(QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE)) |
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#define QEDR_ROCE_MAX_CNQ_SIZE (0x4000) |
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#define QEDR_MAX_PORT (1) |
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#define QEDR_PORT (1) |
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#define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) |
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#define QEDR_ROCE_PKEY_MAX 1 |
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#define QEDR_ROCE_PKEY_TABLE_LEN 1 |
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#define QEDR_ROCE_PKEY_DEFAULT 0xffff |
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struct qedr_pbl { |
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struct list_head list_entry; |
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void *va; |
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dma_addr_t pa; |
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}; |
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struct qedr_ucontext { |
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struct ib_ucontext ibucontext; |
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struct qedr_dev *dev; |
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struct qedr_pd *pd; |
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void __iomem *dpi_addr; |
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struct rdma_user_mmap_entry *db_mmap_entry; |
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u64 dpi_phys_addr; |
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u32 dpi_size; |
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u16 dpi; |
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bool db_rec; |
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u8 edpm_mode; |
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}; |
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union db_prod32 { |
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struct rdma_pwm_val16_data data; |
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u32 raw; |
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}; |
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union db_prod64 { |
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struct rdma_pwm_val32_data data; |
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u64 raw; |
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}; |
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enum qedr_cq_type { |
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QEDR_CQ_TYPE_GSI, |
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QEDR_CQ_TYPE_KERNEL, |
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QEDR_CQ_TYPE_USER, |
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}; |
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struct qedr_pbl_info { |
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u32 num_pbls; |
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u32 num_pbes; |
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u32 pbl_size; |
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u32 pbe_size; |
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bool two_layered; |
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}; |
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struct qedr_userq { |
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struct ib_umem *umem; |
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struct qedr_pbl_info pbl_info; |
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struct qedr_pbl *pbl_tbl; |
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u64 buf_addr; |
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size_t buf_len; |
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/* doorbell recovery */ |
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void __iomem *db_addr; |
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struct qedr_user_db_rec *db_rec_data; |
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struct rdma_user_mmap_entry *db_mmap_entry; |
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void __iomem *db_rec_db2_addr; |
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union db_prod32 db_rec_db2_data; |
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}; |
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struct qedr_cq { |
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struct ib_cq ibcq; |
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enum qedr_cq_type cq_type; |
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u32 sig; |
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u16 icid; |
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/* Lock to protect multiplem CQ's */ |
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spinlock_t cq_lock; |
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u8 arm_flags; |
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struct qed_chain pbl; |
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void __iomem *db_addr; |
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union db_prod64 db; |
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u8 pbl_toggle; |
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union rdma_cqe *latest_cqe; |
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union rdma_cqe *toggle_cqe; |
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u32 cq_cons; |
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struct qedr_userq q; |
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u8 destroyed; |
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u16 cnq_notif; |
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}; |
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struct qedr_pd { |
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struct ib_pd ibpd; |
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u32 pd_id; |
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struct qedr_ucontext *uctx; |
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}; |
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struct qedr_xrcd { |
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struct ib_xrcd ibxrcd; |
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u16 xrcd_id; |
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}; |
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struct qedr_qp_hwq_info { |
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/* WQE Elements */ |
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struct qed_chain pbl; |
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u64 p_phys_addr_tbl; |
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u32 max_sges; |
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/* WQE */ |
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u16 prod; |
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u16 cons; |
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u16 wqe_cons; |
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u16 gsi_cons; |
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u16 max_wr; |
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/* DB */ |
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void __iomem *db; |
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union db_prod32 db_data; |
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void __iomem *iwarp_db2; |
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union db_prod32 iwarp_db2_data; |
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}; |
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#define QEDR_INC_SW_IDX(p_info, index) \ |
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do { \ |
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p_info->index = (p_info->index + 1) & \ |
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qed_chain_get_capacity(p_info->pbl) \ |
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} while (0) |
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struct qedr_srq_hwq_info { |
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u32 max_sges; |
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u32 max_wr; |
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struct qed_chain pbl; |
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u64 p_phys_addr_tbl; |
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u32 wqe_prod; |
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u32 sge_prod; |
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u32 wr_prod_cnt; |
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atomic_t wr_cons_cnt; |
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u32 num_elems; |
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struct rdma_srq_producers *virt_prod_pair_addr; |
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dma_addr_t phy_prod_pair_addr; |
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}; |
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struct qedr_srq { |
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struct ib_srq ibsrq; |
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struct qedr_dev *dev; |
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struct qedr_userq usrq; |
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struct qedr_srq_hwq_info hw_srq; |
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struct ib_umem *prod_umem; |
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u16 srq_id; |
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u32 srq_limit; |
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bool is_xrc; |
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/* lock to protect srq recv post */ |
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spinlock_t lock; |
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}; |
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enum qedr_qp_err_bitmap { |
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QEDR_QP_ERR_SQ_FULL = 1, |
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QEDR_QP_ERR_RQ_FULL = 2, |
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QEDR_QP_ERR_BAD_SR = 4, |
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QEDR_QP_ERR_BAD_RR = 8, |
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QEDR_QP_ERR_SQ_PBL_FULL = 16, |
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QEDR_QP_ERR_RQ_PBL_FULL = 32, |
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}; |
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enum qedr_qp_create_type { |
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QEDR_QP_CREATE_NONE, |
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QEDR_QP_CREATE_USER, |
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QEDR_QP_CREATE_KERNEL, |
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}; |
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enum qedr_iwarp_cm_flags { |
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QEDR_IWARP_CM_WAIT_FOR_CONNECT = BIT(0), |
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QEDR_IWARP_CM_WAIT_FOR_DISCONNECT = BIT(1), |
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}; |
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struct qedr_qp { |
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struct ib_qp ibqp; /* must be first */ |
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struct qedr_dev *dev; |
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struct qedr_qp_hwq_info sq; |
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struct qedr_qp_hwq_info rq; |
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u32 max_inline_data; |
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/* Lock for QP's */ |
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spinlock_t q_lock; |
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struct qedr_cq *sq_cq; |
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struct qedr_cq *rq_cq; |
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struct qedr_srq *srq; |
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enum qed_roce_qp_state state; |
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u32 id; |
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struct qedr_pd *pd; |
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enum ib_qp_type qp_type; |
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enum qedr_qp_create_type create_type; |
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struct qed_rdma_qp *qed_qp; |
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u32 qp_id; |
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u16 icid; |
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u16 mtu; |
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int sgid_idx; |
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u32 rq_psn; |
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u32 sq_psn; |
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u32 qkey; |
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u32 dest_qp_num; |
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/* Relevant to qps created from kernel space only (ULPs) */ |
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u8 prev_wqe_size; |
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u16 wqe_cons; |
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u32 err_bitmap; |
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bool signaled; |
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/* SQ shadow */ |
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struct { |
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u64 wr_id; |
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enum ib_wc_opcode opcode; |
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u32 bytes_len; |
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u8 wqe_size; |
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bool signaled; |
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dma_addr_t icrc_mapping; |
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u32 *icrc; |
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struct qedr_mr *mr; |
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} *wqe_wr_id; |
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/* RQ shadow */ |
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struct { |
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u64 wr_id; |
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struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; |
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u8 wqe_size; |
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u8 smac[ETH_ALEN]; |
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u16 vlan; |
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int rc; |
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} *rqe_wr_id; |
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/* Relevant to qps created from user space only (applications) */ |
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struct qedr_userq usq; |
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struct qedr_userq urq; |
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/* synchronization objects used with iwarp ep */ |
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struct kref refcnt; |
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struct completion iwarp_cm_comp; |
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unsigned long iwarp_cm_flags; /* enum iwarp_cm_flags */ |
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}; |
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struct qedr_ah { |
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struct ib_ah ibah; |
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struct rdma_ah_attr attr; |
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}; |
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enum qedr_mr_type { |
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QEDR_MR_USER, |
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QEDR_MR_KERNEL, |
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QEDR_MR_DMA, |
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QEDR_MR_FRMR, |
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}; |
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struct mr_info { |
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struct qedr_pbl *pbl_table; |
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struct qedr_pbl_info pbl_info; |
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struct list_head free_pbl_list; |
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struct list_head inuse_pbl_list; |
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u32 completed; |
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u32 completed_handled; |
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}; |
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struct qedr_mr { |
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struct ib_mr ibmr; |
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struct ib_umem *umem; |
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struct qed_rdma_register_tid_in_params hw_mr; |
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enum qedr_mr_type type; |
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struct qedr_dev *dev; |
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struct mr_info info; |
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u64 *pages; |
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u32 npages; |
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}; |
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struct qedr_user_mmap_entry { |
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struct rdma_user_mmap_entry rdma_entry; |
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struct qedr_dev *dev; |
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union { |
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u64 io_address; |
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void *address; |
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}; |
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size_t length; |
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u16 dpi; |
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u8 mmap_flag; |
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}; |
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#define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT))) |
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#define QEDR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \ |
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RDMA_CQE_RESPONDER_IMM_FLG_SHIFT) |
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#define QEDR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \ |
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RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT) |
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#define QEDR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \ |
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RDMA_CQE_RESPONDER_INV_FLG_SHIFT) |
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static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info) |
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{ |
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info->cons = (info->cons + 1) % info->max_wr; |
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info->wqe_cons++; |
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} |
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static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info) |
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{ |
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info->prod = (info->prod + 1) % info->max_wr; |
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} |
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static inline int qedr_get_dmac(struct qedr_dev *dev, |
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struct rdma_ah_attr *ah_attr, u8 *mac_addr) |
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{ |
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union ib_gid zero_sgid = { { 0 } }; |
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struct in6_addr in6; |
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const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); |
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u8 *dmac; |
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if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) { |
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DP_ERR(dev, "Local port GID not supported\n"); |
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eth_zero_addr(mac_addr); |
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return -EINVAL; |
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} |
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memcpy(&in6, grh->dgid.raw, sizeof(in6)); |
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dmac = rdma_ah_retrieve_dmac(ah_attr); |
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if (!dmac) |
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return -EINVAL; |
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ether_addr_copy(mac_addr, dmac); |
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return 0; |
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} |
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struct qedr_iw_listener { |
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struct qedr_dev *dev; |
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struct iw_cm_id *cm_id; |
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int backlog; |
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void *qed_handle; |
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}; |
|
|
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struct qedr_iw_ep { |
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struct qedr_dev *dev; |
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struct iw_cm_id *cm_id; |
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struct qedr_qp *qp; |
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void *qed_context; |
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struct kref refcnt; |
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}; |
|
|
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static inline |
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struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext) |
|
{ |
|
return container_of(ibucontext, struct qedr_ucontext, ibucontext); |
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} |
|
|
|
static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev) |
|
{ |
|
return container_of(ibdev, struct qedr_dev, ibdev); |
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} |
|
|
|
static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd) |
|
{ |
|
return container_of(ibpd, struct qedr_pd, ibpd); |
|
} |
|
|
|
static inline struct qedr_xrcd *get_qedr_xrcd(struct ib_xrcd *ibxrcd) |
|
{ |
|
return container_of(ibxrcd, struct qedr_xrcd, ibxrcd); |
|
} |
|
|
|
static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq) |
|
{ |
|
return container_of(ibcq, struct qedr_cq, ibcq); |
|
} |
|
|
|
static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp) |
|
{ |
|
return container_of(ibqp, struct qedr_qp, ibqp); |
|
} |
|
|
|
static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah) |
|
{ |
|
return container_of(ibah, struct qedr_ah, ibah); |
|
} |
|
|
|
static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr) |
|
{ |
|
return container_of(ibmr, struct qedr_mr, ibmr); |
|
} |
|
|
|
static inline struct qedr_srq *get_qedr_srq(struct ib_srq *ibsrq) |
|
{ |
|
return container_of(ibsrq, struct qedr_srq, ibsrq); |
|
} |
|
|
|
static inline bool qedr_qp_has_srq(struct qedr_qp *qp) |
|
{ |
|
return qp->srq; |
|
} |
|
|
|
static inline bool qedr_qp_has_sq(struct qedr_qp *qp) |
|
{ |
|
if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_XRC_TGT) |
|
return false; |
|
|
|
return true; |
|
} |
|
|
|
static inline bool qedr_qp_has_rq(struct qedr_qp *qp) |
|
{ |
|
if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_XRC_INI || |
|
qp->qp_type == IB_QPT_XRC_TGT || qedr_qp_has_srq(qp)) |
|
return false; |
|
|
|
return true; |
|
} |
|
|
|
static inline struct qedr_user_mmap_entry * |
|
get_qedr_mmap_entry(struct rdma_user_mmap_entry *rdma_entry) |
|
{ |
|
return container_of(rdma_entry, struct qedr_user_mmap_entry, |
|
rdma_entry); |
|
} |
|
#endif
|
|
|