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607 lines
13 KiB
607 lines
13 KiB
/* This file is part of the Emulex RoCE Device Driver for |
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* RoCE (RDMA over Converged Ethernet) adapters. |
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* Copyright (C) 2012-2015 Emulex. All rights reserved. |
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* EMULEX and SLI are trademarks of Emulex. |
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* www.emulex.com |
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* |
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* This software is available to you under a choice of one of two licenses. |
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* You may choose to be licensed under the terms of the GNU General Public |
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* License (GPL) Version 2, available from the file COPYING in the main |
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* directory of this source tree, or the BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* - Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the distribution. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* Contact Information: |
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* [email protected] |
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* |
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* Emulex |
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* 3333 Susan Street |
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* Costa Mesa, CA 92626 |
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*/ |
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#ifndef __OCRDMA_H__ |
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#define __OCRDMA_H__ |
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#include <linux/mutex.h> |
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#include <linux/list.h> |
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#include <linux/spinlock.h> |
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#include <linux/pci.h> |
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#include <rdma/ib_verbs.h> |
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#include <rdma/ib_user_verbs.h> |
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#include <rdma/ib_addr.h> |
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#include <be_roce.h> |
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#include "ocrdma_sli.h" |
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#define OCRDMA_ROCE_DRV_VERSION "11.0.0.0" |
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#define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver" |
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#define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA" |
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#define OC_NAME_SH OCRDMA_NODE_DESC "(Skyhawk)" |
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#define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)" |
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#define OC_SKH_DEVICE_PF 0x720 |
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#define OC_SKH_DEVICE_VF 0x728 |
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#define OCRDMA_MAX_AH 512 |
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#define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) |
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#define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo) |
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#define EQ_INTR_PER_SEC_THRSH_HI 150000 |
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#define EQ_INTR_PER_SEC_THRSH_LOW 100000 |
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#define EQ_AIC_MAX_EQD 20 |
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#define EQ_AIC_MIN_EQD 0 |
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void ocrdma_eqd_set_task(struct work_struct *work); |
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struct ocrdma_dev_attr { |
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u8 fw_ver[32]; |
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u32 vendor_id; |
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u32 device_id; |
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u16 max_pd; |
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u16 max_dpp_pds; |
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u16 max_cq; |
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u16 max_cqe; |
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u16 max_qp; |
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u16 max_wqe; |
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u16 max_rqe; |
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u16 max_srq; |
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u32 max_inline_data; |
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int max_send_sge; |
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int max_recv_sge; |
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int max_srq_sge; |
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int max_rdma_sge; |
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int max_mr; |
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u64 max_mr_size; |
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u32 max_num_mr_pbl; |
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int max_mw; |
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int max_map_per_fmr; |
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int max_pages_per_frmr; |
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u16 max_ord_per_qp; |
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u16 max_ird_per_qp; |
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int device_cap_flags; |
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u8 cq_overflow_detect; |
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u8 srq_supported; |
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u32 wqe_size; |
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u32 rqe_size; |
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u32 ird_page_size; |
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u8 local_ca_ack_delay; |
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u8 ird; |
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u8 num_ird_pages; |
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u8 udp_encap; |
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}; |
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struct ocrdma_dma_mem { |
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void *va; |
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dma_addr_t pa; |
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u32 size; |
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}; |
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struct ocrdma_pbl { |
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void *va; |
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dma_addr_t pa; |
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}; |
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struct ocrdma_queue_info { |
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void *va; |
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dma_addr_t dma; |
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u32 size; |
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u16 len; |
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u16 entry_size; /* Size of an element in the queue */ |
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u16 id; /* qid, where to ring the doorbell. */ |
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u16 head, tail; |
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bool created; |
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}; |
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struct ocrdma_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ |
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u32 prev_eqd; |
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u64 eq_intr_cnt; |
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u64 prev_eq_intr_cnt; |
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}; |
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struct ocrdma_eq { |
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struct ocrdma_queue_info q; |
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u32 vector; |
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int cq_cnt; |
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struct ocrdma_dev *dev; |
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char irq_name[32]; |
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struct ocrdma_aic_obj aic_obj; |
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}; |
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struct ocrdma_mq { |
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struct ocrdma_queue_info sq; |
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struct ocrdma_queue_info cq; |
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bool rearm_cq; |
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}; |
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struct mqe_ctx { |
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struct mutex lock; /* for serializing mailbox commands on MQ */ |
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wait_queue_head_t cmd_wait; |
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u32 tag; |
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u16 cqe_status; |
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u16 ext_status; |
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bool cmd_done; |
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bool fw_error_state; |
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}; |
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struct ocrdma_hw_mr { |
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u32 lkey; |
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u8 fr_mr; |
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u8 remote_atomic; |
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u8 remote_rd; |
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u8 remote_wr; |
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u8 local_rd; |
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u8 local_wr; |
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u8 mw_bind; |
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u8 rsvd; |
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u64 len; |
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struct ocrdma_pbl *pbl_table; |
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u32 num_pbls; |
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u32 num_pbes; |
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u32 pbl_size; |
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u32 pbe_size; |
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u64 va; |
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}; |
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struct ocrdma_mr { |
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struct ib_mr ibmr; |
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struct ib_umem *umem; |
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struct ocrdma_hw_mr hwmr; |
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u64 *pages; |
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u32 npages; |
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}; |
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struct ocrdma_stats { |
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u8 type; |
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struct ocrdma_dev *dev; |
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}; |
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struct ocrdma_pd_resource_mgr { |
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u32 pd_norm_start; |
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u16 pd_norm_count; |
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u16 pd_norm_thrsh; |
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u16 max_normal_pd; |
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u32 pd_dpp_start; |
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u16 pd_dpp_count; |
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u16 pd_dpp_thrsh; |
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u16 max_dpp_pd; |
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u16 dpp_page_index; |
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unsigned long *pd_norm_bitmap; |
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unsigned long *pd_dpp_bitmap; |
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bool pd_prealloc_valid; |
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}; |
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struct stats_mem { |
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struct ocrdma_mqe mqe; |
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void *va; |
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dma_addr_t pa; |
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u32 size; |
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char *debugfs_mem; |
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}; |
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struct phy_info { |
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u16 auto_speeds_supported; |
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u16 fixed_speeds_supported; |
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u16 phy_type; |
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u16 interface_type; |
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}; |
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enum ocrdma_flags { |
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OCRDMA_FLAGS_LINK_STATUS_INIT = 0x01 |
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}; |
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struct ocrdma_dev { |
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struct ib_device ibdev; |
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struct ocrdma_dev_attr attr; |
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struct mutex dev_lock; /* provides syncronise access to device data */ |
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spinlock_t flush_q_lock ____cacheline_aligned; |
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struct ocrdma_cq **cq_tbl; |
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struct ocrdma_qp **qp_tbl; |
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struct ocrdma_eq *eq_tbl; |
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int eq_cnt; |
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struct delayed_work eqd_work; |
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u16 base_eqid; |
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u16 max_eq; |
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/* provided synchronization to sgid table for |
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* updating gid entries triggered by notifier. |
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*/ |
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spinlock_t sgid_lock; |
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int gsi_qp_created; |
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struct ocrdma_cq *gsi_sqcq; |
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struct ocrdma_cq *gsi_rqcq; |
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struct { |
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struct ocrdma_av *va; |
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dma_addr_t pa; |
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u32 size; |
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u32 num_ah; |
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/* provide synchronization for av |
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* entry allocations. |
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*/ |
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spinlock_t lock; |
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u32 ahid; |
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struct ocrdma_pbl pbl; |
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} av_tbl; |
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void *mbx_cmd; |
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struct ocrdma_mq mq; |
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struct mqe_ctx mqe_ctx; |
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struct be_dev_info nic_info; |
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struct phy_info phy; |
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char model_number[32]; |
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u32 hba_port_num; |
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struct list_head entry; |
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int id; |
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u64 *stag_arr; |
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u8 sl; /* service level */ |
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bool pfc_state; |
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atomic_t update_sl; |
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u16 pvid; |
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u32 asic_id; |
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u32 flags; |
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ulong last_stats_time; |
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struct mutex stats_lock; /* provide synch for debugfs operations */ |
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struct stats_mem stats_mem; |
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struct ocrdma_stats rsrc_stats; |
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struct ocrdma_stats rx_stats; |
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struct ocrdma_stats wqe_stats; |
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struct ocrdma_stats tx_stats; |
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struct ocrdma_stats db_err_stats; |
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struct ocrdma_stats tx_qp_err_stats; |
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struct ocrdma_stats rx_qp_err_stats; |
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struct ocrdma_stats tx_dbg_stats; |
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struct ocrdma_stats rx_dbg_stats; |
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struct ocrdma_stats driver_stats; |
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struct ocrdma_stats reset_stats; |
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struct dentry *dir; |
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atomic_t async_err_stats[OCRDMA_MAX_ASYNC_ERRORS]; |
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atomic_t cqe_err_stats[OCRDMA_MAX_CQE_ERR]; |
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struct ocrdma_pd_resource_mgr *pd_mgr; |
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}; |
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struct ocrdma_cq { |
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struct ib_cq ibcq; |
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struct ocrdma_cqe *va; |
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u32 phase; |
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u32 getp; /* pointer to pending wrs to |
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* return to stack, wrap arounds |
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* at max_hw_cqe |
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*/ |
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u32 max_hw_cqe; |
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bool phase_change; |
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spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization |
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* to cq polling |
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*/ |
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/* syncronizes cq completion handler invoked from multiple context */ |
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spinlock_t comp_handler_lock ____cacheline_aligned; |
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u16 id; |
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u16 eqn; |
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struct ocrdma_ucontext *ucontext; |
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dma_addr_t pa; |
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u32 len; |
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u32 cqe_cnt; |
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/* head of all qp's sq and rq for which cqes need to be flushed |
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* by the software. |
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*/ |
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struct list_head sq_head, rq_head; |
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}; |
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struct ocrdma_pd { |
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struct ib_pd ibpd; |
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struct ocrdma_ucontext *uctx; |
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u32 id; |
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int num_dpp_qp; |
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u32 dpp_page; |
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bool dpp_enabled; |
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}; |
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struct ocrdma_ah { |
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struct ib_ah ibah; |
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struct ocrdma_av *av; |
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u16 sgid_index; |
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u32 id; |
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u8 hdr_type; |
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}; |
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struct ocrdma_qp_hwq_info { |
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u8 *va; /* virtual address */ |
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u32 max_sges; |
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u32 head, tail; |
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u32 entry_size; |
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u32 max_cnt; |
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u32 max_wqe_idx; |
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u16 dbid; /* qid, where to ring the doorbell. */ |
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u32 len; |
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dma_addr_t pa; |
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}; |
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struct ocrdma_srq { |
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struct ib_srq ibsrq; |
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u8 __iomem *db; |
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struct ocrdma_qp_hwq_info rq; |
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u64 *rqe_wr_id_tbl; |
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u32 *idx_bit_fields; |
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u32 bit_fields_len; |
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/* provide synchronization to multiple context(s) posting rqe */ |
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spinlock_t q_lock ____cacheline_aligned; |
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struct ocrdma_pd *pd; |
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u32 id; |
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}; |
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struct ocrdma_qp { |
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struct ib_qp ibqp; |
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u8 __iomem *sq_db; |
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struct ocrdma_qp_hwq_info sq; |
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struct { |
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uint64_t wrid; |
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uint16_t dpp_wqe_idx; |
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uint16_t dpp_wqe; |
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uint8_t signaled; |
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uint8_t rsvd[3]; |
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} *wqe_wr_id_tbl; |
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u32 max_inline_data; |
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/* provide synchronization to multiple context(s) posting wqe, rqe */ |
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spinlock_t q_lock ____cacheline_aligned; |
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struct ocrdma_cq *sq_cq; |
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/* list maintained per CQ to flush SQ errors */ |
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struct list_head sq_entry; |
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u8 __iomem *rq_db; |
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struct ocrdma_qp_hwq_info rq; |
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u64 *rqe_wr_id_tbl; |
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struct ocrdma_cq *rq_cq; |
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struct ocrdma_srq *srq; |
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/* list maintained per CQ to flush RQ errors */ |
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struct list_head rq_entry; |
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enum ocrdma_qp_state state; /* QP state */ |
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int cap_flags; |
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u32 max_ord, max_ird; |
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u32 id; |
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struct ocrdma_pd *pd; |
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enum ib_qp_type qp_type; |
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int sgid_idx; |
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u32 qkey; |
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bool dpp_enabled; |
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u8 *ird_q_va; |
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bool signaled; |
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}; |
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struct ocrdma_ucontext { |
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struct ib_ucontext ibucontext; |
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struct list_head mm_head; |
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struct mutex mm_list_lock; /* protects list entries of mm type */ |
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struct ocrdma_pd *cntxt_pd; |
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int pd_in_use; |
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struct { |
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u32 *va; |
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dma_addr_t pa; |
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u32 len; |
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} ah_tbl; |
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}; |
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struct ocrdma_mm { |
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struct { |
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u64 phy_addr; |
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unsigned long len; |
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} key; |
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struct list_head entry; |
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}; |
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static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev) |
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{ |
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return container_of(ibdev, struct ocrdma_dev, ibdev); |
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} |
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static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext |
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*ibucontext) |
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{ |
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return container_of(ibucontext, struct ocrdma_ucontext, ibucontext); |
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} |
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static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd) |
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{ |
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return container_of(ibpd, struct ocrdma_pd, ibpd); |
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} |
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static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq) |
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{ |
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return container_of(ibcq, struct ocrdma_cq, ibcq); |
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} |
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static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp) |
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{ |
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return container_of(ibqp, struct ocrdma_qp, ibqp); |
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} |
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static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr) |
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{ |
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return container_of(ibmr, struct ocrdma_mr, ibmr); |
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} |
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static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah) |
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{ |
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return container_of(ibah, struct ocrdma_ah, ibah); |
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} |
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static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq) |
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{ |
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return container_of(ibsrq, struct ocrdma_srq, ibsrq); |
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} |
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static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe) |
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{ |
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int cqe_valid; |
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cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID; |
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return (cqe_valid == cq->phase); |
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} |
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static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe) |
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{ |
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return (le32_to_cpu(cqe->flags_status_srcqpn) & |
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OCRDMA_CQE_QTYPE) ? 0 : 1; |
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} |
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static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe) |
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{ |
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return (le32_to_cpu(cqe->flags_status_srcqpn) & |
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OCRDMA_CQE_INVALIDATE) ? 1 : 0; |
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} |
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static inline int is_cqe_imm(struct ocrdma_cqe *cqe) |
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{ |
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return (le32_to_cpu(cqe->flags_status_srcqpn) & |
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OCRDMA_CQE_IMM) ? 1 : 0; |
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} |
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static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe) |
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{ |
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return (le32_to_cpu(cqe->flags_status_srcqpn) & |
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OCRDMA_CQE_WRITE_IMM) ? 1 : 0; |
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} |
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static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev, |
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struct rdma_ah_attr *ah_attr, u8 *mac_addr) |
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{ |
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struct in6_addr in6; |
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memcpy(&in6, rdma_ah_read_grh(ah_attr)->dgid.raw, sizeof(in6)); |
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if (rdma_is_multicast_addr(&in6)) |
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rdma_get_mcast_mac(&in6, mac_addr); |
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else if (rdma_link_local_addr(&in6)) |
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rdma_get_ll_mac(&in6, mac_addr); |
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else |
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memcpy(mac_addr, ah_attr->roce.dmac, ETH_ALEN); |
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return 0; |
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} |
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static inline char *hca_name(struct ocrdma_dev *dev) |
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{ |
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switch (dev->nic_info.pdev->device) { |
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case OC_SKH_DEVICE_PF: |
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case OC_SKH_DEVICE_VF: |
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return OC_NAME_SH; |
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default: |
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return OC_NAME_UNKNOWN; |
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} |
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} |
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static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev, |
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int eqid) |
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{ |
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int indx; |
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for (indx = 0; indx < dev->eq_cnt; indx++) { |
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if (dev->eq_tbl[indx].q.id == eqid) |
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return indx; |
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} |
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return -EINVAL; |
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} |
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static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev) |
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{ |
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if (dev->nic_info.dev_family == 0xF && !dev->asic_id) { |
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pci_read_config_dword( |
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dev->nic_info.pdev, |
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OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id); |
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} |
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return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >> |
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OCRDMA_SLI_ASIC_GEN_NUM_SHIFT; |
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} |
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static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio) |
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{ |
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return *(pfc + prio); |
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} |
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static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio) |
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{ |
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return *(app_prio + prio); |
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} |
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static inline u8 ocrdma_is_enabled_and_synced(u32 state) |
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{ /* May also be used to interpret TC-state, QCN-state |
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* Appl-state and Logical-link-state in future. |
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*/ |
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return (state & OCRDMA_STATE_FLAG_ENABLED) && |
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(state & OCRDMA_STATE_FLAG_SYNC); |
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} |
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static inline u8 ocrdma_get_ae_link_state(u32 ae_state) |
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{ |
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return ((ae_state & OCRDMA_AE_LSC_LS_MASK) >> OCRDMA_AE_LSC_LS_SHIFT); |
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} |
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static inline bool ocrdma_is_udp_encap_supported(struct ocrdma_dev *dev) |
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{ |
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return (dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV4) || |
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(dev->attr.udp_encap & OCRDMA_L3_TYPE_IPV6); |
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} |
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#endif
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