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458 lines
15 KiB
458 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2012 Invensense, Inc. |
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*/ |
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#ifndef INV_MPU_IIO_H_ |
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#define INV_MPU_IIO_H_ |
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#include <linux/i2c.h> |
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#include <linux/i2c-mux.h> |
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#include <linux/mutex.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/buffer.h> |
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#include <linux/regmap.h> |
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#include <linux/iio/sysfs.h> |
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#include <linux/iio/kfifo_buf.h> |
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#include <linux/iio/trigger.h> |
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#include <linux/iio/triggered_buffer.h> |
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#include <linux/iio/trigger_consumer.h> |
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#include <linux/platform_data/invensense_mpu6050.h> |
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/** |
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* struct inv_mpu6050_reg_map - Notable registers. |
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* @sample_rate_div: Divider applied to gyro output rate. |
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* @lpf: Configures internal low pass filter. |
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* @accel_lpf: Configures accelerometer low pass filter. |
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* @user_ctrl: Enables/resets the FIFO. |
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* @fifo_en: Determines which data will appear in FIFO. |
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* @gyro_config: gyro config register. |
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* @accl_config: accel config register |
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* @fifo_count_h: Upper byte of FIFO count. |
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* @fifo_r_w: FIFO register. |
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* @raw_gyro: Address of first gyro register. |
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* @raw_accl: Address of first accel register. |
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* @temperature: temperature register |
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* @int_enable: Interrupt enable register. |
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* @int_status: Interrupt status register. |
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* @pwr_mgmt_1: Controls chip's power state and clock source. |
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* @pwr_mgmt_2: Controls power state of individual sensors. |
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* @int_pin_cfg; Controls interrupt pin configuration. |
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* @accl_offset: Controls the accelerometer calibration offset. |
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* @gyro_offset: Controls the gyroscope calibration offset. |
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* @i2c_if: Controls the i2c interface |
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*/ |
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struct inv_mpu6050_reg_map { |
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u8 sample_rate_div; |
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u8 lpf; |
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u8 accel_lpf; |
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u8 user_ctrl; |
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u8 fifo_en; |
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u8 gyro_config; |
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u8 accl_config; |
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u8 fifo_count_h; |
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u8 fifo_r_w; |
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u8 raw_gyro; |
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u8 raw_accl; |
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u8 temperature; |
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u8 int_enable; |
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u8 int_status; |
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u8 pwr_mgmt_1; |
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u8 pwr_mgmt_2; |
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u8 int_pin_cfg; |
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u8 accl_offset; |
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u8 gyro_offset; |
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u8 i2c_if; |
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}; |
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/*device enum */ |
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enum inv_devices { |
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INV_MPU6050, |
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INV_MPU6500, |
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INV_MPU6515, |
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INV_MPU6880, |
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INV_MPU6000, |
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INV_MPU9150, |
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INV_MPU9250, |
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INV_MPU9255, |
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INV_ICM20608, |
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INV_ICM20609, |
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INV_ICM20689, |
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INV_ICM20602, |
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INV_ICM20690, |
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INV_IAM20680, |
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INV_NUM_PARTS |
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}; |
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/* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer */ |
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#define INV_MPU6050_SENSOR_ACCL BIT(0) |
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#define INV_MPU6050_SENSOR_GYRO BIT(1) |
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#define INV_MPU6050_SENSOR_TEMP BIT(2) |
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#define INV_MPU6050_SENSOR_MAGN BIT(3) |
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/** |
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* struct inv_mpu6050_chip_config - Cached chip configuration data. |
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* @clk: selected chip clock |
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* @fsr: Full scale range. |
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* @lpf: Digital low pass filter frequency. |
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* @accl_fs: accel full scale range. |
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* @accl_en: accel engine enabled |
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* @gyro_en: gyro engine enabled |
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* @temp_en: temperature sensor enabled |
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* @magn_en: magn engine (i2c master) enabled |
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* @accl_fifo_enable: enable accel data output |
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* @gyro_fifo_enable: enable gyro data output |
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* @temp_fifo_enable: enable temp data output |
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* @magn_fifo_enable: enable magn data output |
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* @divider: chip sample rate divider (sample rate divider - 1) |
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*/ |
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struct inv_mpu6050_chip_config { |
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unsigned int clk:3; |
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unsigned int fsr:2; |
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unsigned int lpf:3; |
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unsigned int accl_fs:2; |
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unsigned int accl_en:1; |
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unsigned int gyro_en:1; |
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unsigned int temp_en:1; |
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unsigned int magn_en:1; |
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unsigned int accl_fifo_enable:1; |
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unsigned int gyro_fifo_enable:1; |
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unsigned int temp_fifo_enable:1; |
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unsigned int magn_fifo_enable:1; |
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u8 divider; |
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u8 user_ctrl; |
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}; |
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/* |
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* Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8. |
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* May be less if fewer channels are enabled, as long as the timestamp |
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* remains 8 byte aligned |
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*/ |
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#define INV_MPU6050_OUTPUT_DATA_SIZE 32 |
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/** |
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* struct inv_mpu6050_hw - Other important hardware information. |
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* @whoami: Self identification byte from WHO_AM_I register |
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* @name: name of the chip. |
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* @reg: register map of the chip. |
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* @config: configuration of the chip. |
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* @fifo_size: size of the FIFO in bytes. |
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* @temp: offset and scale to apply to raw temperature. |
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*/ |
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struct inv_mpu6050_hw { |
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u8 whoami; |
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u8 *name; |
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const struct inv_mpu6050_reg_map *reg; |
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const struct inv_mpu6050_chip_config *config; |
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size_t fifo_size; |
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struct { |
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int offset; |
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int scale; |
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} temp; |
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}; |
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/* |
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* struct inv_mpu6050_state - Driver state variables. |
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* @lock: Chip access lock. |
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* @trig: IIO trigger. |
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* @chip_config: Cached attribute information. |
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* @reg: Map of important registers. |
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* @hw: Other hardware-specific information. |
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* @chip_type: chip type. |
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* @plat_data: platform data (deprecated in favor of @orientation). |
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* @orientation: sensor chip orientation relative to main hardware. |
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* @map regmap pointer. |
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* @irq interrupt number. |
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* @irq_mask the int_pin_cfg mask to configure interrupt type. |
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* @chip_period: chip internal period estimation (~1kHz). |
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* @it_timestamp: timestamp from previous interrupt. |
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* @data_timestamp: timestamp for next data sample. |
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* @vdd_supply: VDD voltage regulator for the chip. |
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* @vddio_supply I/O voltage regulator for the chip. |
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* @magn_disabled: magnetometer disabled for backward compatibility reason. |
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* @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss. |
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* @magn_orient: magnetometer sensor chip orientation if available. |
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* @suspended_sensors: sensors mask of sensors turned off for suspend |
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* @data: dma safe buffer used for bulk reads. |
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*/ |
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struct inv_mpu6050_state { |
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struct mutex lock; |
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struct iio_trigger *trig; |
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struct inv_mpu6050_chip_config chip_config; |
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const struct inv_mpu6050_reg_map *reg; |
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const struct inv_mpu6050_hw *hw; |
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enum inv_devices chip_type; |
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struct i2c_mux_core *muxc; |
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struct i2c_client *mux_client; |
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struct inv_mpu6050_platform_data plat_data; |
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struct iio_mount_matrix orientation; |
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struct regmap *map; |
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int irq; |
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u8 irq_mask; |
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unsigned skip_samples; |
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s64 chip_period; |
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s64 it_timestamp; |
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s64 data_timestamp; |
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struct regulator *vdd_supply; |
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struct regulator *vddio_supply; |
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bool magn_disabled; |
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s32 magn_raw_to_gauss[3]; |
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struct iio_mount_matrix magn_orient; |
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unsigned int suspended_sensors; |
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u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] ____cacheline_aligned; |
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}; |
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/*register and associated bit definition*/ |
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#define INV_MPU6050_REG_ACCEL_OFFSET 0x06 |
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#define INV_MPU6050_REG_GYRO_OFFSET 0x13 |
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#define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 |
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#define INV_MPU6050_REG_CONFIG 0x1A |
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#define INV_MPU6050_REG_GYRO_CONFIG 0x1B |
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#define INV_MPU6050_REG_ACCEL_CONFIG 0x1C |
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#define INV_MPU6050_REG_FIFO_EN 0x23 |
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#define INV_MPU6050_BIT_SLAVE_0 0x01 |
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#define INV_MPU6050_BIT_SLAVE_1 0x02 |
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#define INV_MPU6050_BIT_SLAVE_2 0x04 |
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#define INV_MPU6050_BIT_ACCEL_OUT 0x08 |
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#define INV_MPU6050_BITS_GYRO_OUT 0x70 |
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#define INV_MPU6050_BIT_TEMP_OUT 0x80 |
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#define INV_MPU6050_REG_I2C_MST_CTRL 0x24 |
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#define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D |
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#define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10 |
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#define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20 |
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#define INV_MPU6050_BIT_WAIT_FOR_ES 0x40 |
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#define INV_MPU6050_BIT_MULT_MST_EN 0x80 |
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/* control I2C slaves from 0 to 3 */ |
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#define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x)) |
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#define INV_MPU6050_BIT_I2C_SLV_RNW 0x80 |
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#define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x)) |
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#define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x)) |
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#define INV_MPU6050_BIT_SLV_GRP 0x10 |
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#define INV_MPU6050_BIT_SLV_REG_DIS 0x20 |
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#define INV_MPU6050_BIT_SLV_BYTE_SW 0x40 |
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#define INV_MPU6050_BIT_SLV_EN 0x80 |
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/* I2C master delay register */ |
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#define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34 |
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#define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F) |
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#define INV_MPU6050_REG_I2C_MST_STATUS 0x36 |
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#define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01 |
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#define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02 |
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#define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04 |
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#define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08 |
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#define INV_MPU6050_REG_INT_ENABLE 0x38 |
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#define INV_MPU6050_BIT_DATA_RDY_EN 0x01 |
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#define INV_MPU6050_BIT_DMP_INT_EN 0x02 |
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#define INV_MPU6050_REG_RAW_ACCEL 0x3B |
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#define INV_MPU6050_REG_TEMPERATURE 0x41 |
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#define INV_MPU6050_REG_RAW_GYRO 0x43 |
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#define INV_MPU6050_REG_INT_STATUS 0x3A |
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#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10 |
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#define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01 |
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#define INV_MPU6050_REG_EXT_SENS_DATA 0x49 |
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/* I2C slaves data output from 0 to 3 */ |
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#define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x)) |
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#define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67 |
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#define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01 |
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#define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02 |
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#define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04 |
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#define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08 |
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#define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80 |
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#define INV_MPU6050_REG_SIGNAL_PATH_RESET 0x68 |
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#define INV_MPU6050_BIT_TEMP_RST BIT(0) |
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#define INV_MPU6050_BIT_ACCEL_RST BIT(1) |
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#define INV_MPU6050_BIT_GYRO_RST BIT(2) |
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#define INV_MPU6050_REG_USER_CTRL 0x6A |
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#define INV_MPU6050_BIT_SIG_COND_RST 0x01 |
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#define INV_MPU6050_BIT_FIFO_RST 0x04 |
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#define INV_MPU6050_BIT_DMP_RST 0x08 |
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#define INV_MPU6050_BIT_I2C_MST_EN 0x20 |
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#define INV_MPU6050_BIT_FIFO_EN 0x40 |
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#define INV_MPU6050_BIT_DMP_EN 0x80 |
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#define INV_MPU6050_BIT_I2C_IF_DIS 0x10 |
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#define INV_MPU6050_REG_PWR_MGMT_1 0x6B |
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#define INV_MPU6050_BIT_H_RESET 0x80 |
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#define INV_MPU6050_BIT_SLEEP 0x40 |
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#define INV_MPU6050_BIT_TEMP_DIS 0x08 |
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#define INV_MPU6050_BIT_CLK_MASK 0x7 |
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#define INV_MPU6050_REG_PWR_MGMT_2 0x6C |
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#define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 |
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#define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 |
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/* ICM20602 register */ |
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#define INV_ICM20602_REG_I2C_IF 0x70 |
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#define INV_ICM20602_BIT_I2C_IF_DIS 0x40 |
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#define INV_MPU6050_REG_FIFO_COUNT_H 0x72 |
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#define INV_MPU6050_REG_FIFO_R_W 0x74 |
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#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 |
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#define INV_MPU6050_FIFO_COUNT_BYTE 2 |
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/* MPU9X50 9-axis magnetometer */ |
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#define INV_MPU9X50_BYTES_MAGN 7 |
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/* FIFO temperature sample size */ |
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#define INV_MPU6050_BYTES_PER_TEMP_SENSOR 2 |
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/* mpu6500 registers */ |
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#define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D |
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#define INV_ICM20689_BITS_FIFO_SIZE_MAX 0xC0 |
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#define INV_MPU6500_REG_ACCEL_OFFSET 0x77 |
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/* delay time in milliseconds */ |
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#define INV_MPU6050_POWER_UP_TIME 100 |
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#define INV_MPU6050_TEMP_UP_TIME 100 |
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#define INV_MPU6050_ACCEL_UP_TIME 20 |
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#define INV_MPU6050_GYRO_UP_TIME 35 |
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#define INV_MPU6050_GYRO_DOWN_TIME 150 |
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#define INV_MPU6050_SUSPEND_DELAY_MS 2000 |
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/* delay time in microseconds */ |
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#define INV_MPU6050_REG_UP_TIME_MIN 5000 |
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#define INV_MPU6050_REG_UP_TIME_MAX 10000 |
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#define INV_MPU6050_TEMP_OFFSET 12420 |
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#define INV_MPU6050_TEMP_SCALE 2941176 |
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#define INV_MPU6050_MAX_GYRO_FS_PARAM 3 |
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#define INV_MPU6050_MAX_ACCL_FS_PARAM 3 |
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#define INV_MPU6050_THREE_AXIS 3 |
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#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 |
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#define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT 2 |
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#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 |
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#define INV_MPU6500_TEMP_OFFSET 7011 |
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#define INV_MPU6500_TEMP_SCALE 2995178 |
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#define INV_ICM20608_TEMP_OFFSET 8170 |
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#define INV_ICM20608_TEMP_SCALE 3059976 |
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#define INV_MPU6050_REG_INT_PIN_CFG 0x37 |
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#define INV_MPU6050_ACTIVE_HIGH 0x00 |
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#define INV_MPU6050_ACTIVE_LOW 0x80 |
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/* enable level triggering */ |
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#define INV_MPU6050_LATCH_INT_EN 0x20 |
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#define INV_MPU6050_BIT_BYPASS_EN 0x2 |
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/* Allowed timestamp period jitter in percent */ |
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#define INV_MPU6050_TS_PERIOD_JITTER 4 |
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/* init parameters */ |
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#define INV_MPU6050_MAX_FIFO_RATE 1000 |
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#define INV_MPU6050_MIN_FIFO_RATE 4 |
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/* chip internal frequency: 1KHz */ |
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#define INV_MPU6050_INTERNAL_FREQ_HZ 1000 |
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/* return the frequency divider (chip sample rate divider + 1) */ |
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#define INV_MPU6050_FREQ_DIVIDER(st) \ |
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((st)->chip_config.divider + 1) |
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/* chip sample rate divider to fifo rate */ |
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#define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \ |
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((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1) |
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#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \ |
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(INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1)) |
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#define INV_MPU6050_REG_WHOAMI 117 |
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#define INV_MPU6000_WHOAMI_VALUE 0x68 |
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#define INV_MPU6050_WHOAMI_VALUE 0x68 |
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#define INV_MPU6500_WHOAMI_VALUE 0x70 |
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#define INV_MPU6880_WHOAMI_VALUE 0x78 |
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#define INV_MPU9150_WHOAMI_VALUE 0x68 |
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#define INV_MPU9250_WHOAMI_VALUE 0x71 |
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#define INV_MPU9255_WHOAMI_VALUE 0x73 |
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#define INV_MPU6515_WHOAMI_VALUE 0x74 |
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#define INV_ICM20608_WHOAMI_VALUE 0xAF |
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#define INV_ICM20609_WHOAMI_VALUE 0xA6 |
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#define INV_ICM20689_WHOAMI_VALUE 0x98 |
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#define INV_ICM20602_WHOAMI_VALUE 0x12 |
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#define INV_ICM20690_WHOAMI_VALUE 0x20 |
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#define INV_IAM20680_WHOAMI_VALUE 0xA9 |
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/* scan element definition for generic MPU6xxx devices */ |
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enum inv_mpu6050_scan { |
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INV_MPU6050_SCAN_ACCL_X, |
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INV_MPU6050_SCAN_ACCL_Y, |
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INV_MPU6050_SCAN_ACCL_Z, |
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INV_MPU6050_SCAN_TEMP, |
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INV_MPU6050_SCAN_GYRO_X, |
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INV_MPU6050_SCAN_GYRO_Y, |
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INV_MPU6050_SCAN_GYRO_Z, |
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INV_MPU6050_SCAN_TIMESTAMP, |
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INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1, |
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INV_MPU9X50_SCAN_MAGN_Y, |
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INV_MPU9X50_SCAN_MAGN_Z, |
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INV_MPU9X50_SCAN_TIMESTAMP, |
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}; |
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enum inv_mpu6050_filter_e { |
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INV_MPU6050_FILTER_NOLPF2 = 0, |
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INV_MPU6050_FILTER_200HZ, |
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INV_MPU6050_FILTER_100HZ, |
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INV_MPU6050_FILTER_45HZ, |
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INV_MPU6050_FILTER_20HZ, |
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INV_MPU6050_FILTER_10HZ, |
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INV_MPU6050_FILTER_5HZ, |
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INV_MPU6050_FILTER_NOLPF, |
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NUM_MPU6050_FILTER |
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}; |
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/* IIO attribute address */ |
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enum INV_MPU6050_IIO_ATTR_ADDR { |
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ATTR_GYRO_MATRIX, |
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ATTR_ACCL_MATRIX, |
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}; |
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enum inv_mpu6050_accl_fs_e { |
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INV_MPU6050_FS_02G = 0, |
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INV_MPU6050_FS_04G, |
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INV_MPU6050_FS_08G, |
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INV_MPU6050_FS_16G, |
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NUM_ACCL_FSR |
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}; |
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enum inv_mpu6050_fsr_e { |
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INV_MPU6050_FSR_250DPS = 0, |
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INV_MPU6050_FSR_500DPS, |
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INV_MPU6050_FSR_1000DPS, |
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INV_MPU6050_FSR_2000DPS, |
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NUM_MPU6050_FSR |
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}; |
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enum inv_mpu6050_clock_sel_e { |
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INV_CLK_INTERNAL = 0, |
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INV_CLK_PLL, |
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NUM_CLK |
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}; |
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irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); |
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int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); |
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int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable); |
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int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, |
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unsigned int mask); |
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int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); |
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int inv_mpu_acpi_create_mux_client(struct i2c_client *client); |
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void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); |
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int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, |
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int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); |
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extern const struct dev_pm_ops inv_mpu_pmops; |
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#endif
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