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387 lines
10 KiB
387 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Palmchip bk3710 IDE controller |
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* |
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* Copyright (C) 2006 Texas Instruments. |
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* Copyright (C) 2007 MontaVista Software, Inc., <[email protected]> |
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* |
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* ---------------------------------------------------------------------------- |
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* |
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* ---------------------------------------------------------------------------- |
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*/ |
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#include <linux/types.h> |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/ioport.h> |
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#include <linux/ide.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/clk.h> |
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#include <linux/platform_device.h> |
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/* Offset of the primary interface registers */ |
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#define IDE_PALM_ATA_PRI_REG_OFFSET 0x1F0 |
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/* Primary Control Offset */ |
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#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6 |
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#define BK3710_BMICP 0x00 |
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#define BK3710_BMISP 0x02 |
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#define BK3710_BMIDTP 0x04 |
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#define BK3710_IDETIMP 0x40 |
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#define BK3710_IDESTATUS 0x47 |
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#define BK3710_UDMACTL 0x48 |
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#define BK3710_MISCCTL 0x50 |
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#define BK3710_REGSTB 0x54 |
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#define BK3710_REGRCVR 0x58 |
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#define BK3710_DATSTB 0x5C |
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#define BK3710_DATRCVR 0x60 |
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#define BK3710_DMASTB 0x64 |
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#define BK3710_DMARCVR 0x68 |
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#define BK3710_UDMASTB 0x6C |
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#define BK3710_UDMATRP 0x70 |
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#define BK3710_UDMAENV 0x74 |
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#define BK3710_IORDYTMP 0x78 |
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static unsigned ideclk_period; /* in nanoseconds */ |
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struct palm_bk3710_udmatiming { |
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unsigned int rptime; /* tRP -- Ready to pause time (nsec) */ |
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unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */ |
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/* tENV is always a minimum of 20 nsec */ |
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}; |
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static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = { |
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{ 160, 240 / 2 }, /* UDMA Mode 0 */ |
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{ 125, 160 / 2 }, /* UDMA Mode 1 */ |
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{ 100, 120 / 2 }, /* UDMA Mode 2 */ |
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{ 100, 90 / 2 }, /* UDMA Mode 3 */ |
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{ 100, 60 / 2 }, /* UDMA Mode 4 */ |
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{ 85, 40 / 2 }, /* UDMA Mode 5 */ |
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}; |
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static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, |
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unsigned int mode) |
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{ |
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u8 tenv, trp, t0; |
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u32 val32; |
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u16 val16; |
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/* DMA Data Setup */ |
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t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime, |
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ideclk_period) - 1; |
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tenv = DIV_ROUND_UP(20, ideclk_period) - 1; |
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trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime, |
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ideclk_period) - 1; |
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/* udmastb Ultra DMA Access Strobe Width */ |
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val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (t0 << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_UDMASTB); |
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/* udmatrp Ultra DMA Ready to Pause Time */ |
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val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (trp << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_UDMATRP); |
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/* udmaenv Ultra DMA envelop Time */ |
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val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (tenv << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_UDMAENV); |
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/* Enable UDMA for Device */ |
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val16 = readw(base + BK3710_UDMACTL) | (1 << dev); |
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writew(val16, base + BK3710_UDMACTL); |
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} |
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static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev, |
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unsigned short min_cycle, |
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unsigned int mode) |
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{ |
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u8 td, tkw, t0; |
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u32 val32; |
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u16 val16; |
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struct ide_timing *t; |
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int cycletime; |
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t = ide_timing_find_mode(mode); |
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cycletime = max_t(int, t->cycle, min_cycle); |
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/* DMA Data Setup */ |
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t0 = DIV_ROUND_UP(cycletime, ideclk_period); |
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td = DIV_ROUND_UP(t->active, ideclk_period); |
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tkw = t0 - td - 1; |
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td -= 1; |
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val32 = readl(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (td << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_DMASTB); |
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val32 = readl(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (tkw << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_DMARCVR); |
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/* Disable UDMA for Device */ |
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val16 = readw(base + BK3710_UDMACTL) & ~(1 << dev); |
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writew(val16, base + BK3710_UDMACTL); |
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} |
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static void palm_bk3710_setpiomode(void __iomem *base, ide_drive_t *mate, |
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unsigned int dev, unsigned int cycletime, |
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unsigned int mode) |
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{ |
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u8 t2, t2i, t0; |
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u32 val32; |
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struct ide_timing *t; |
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t = ide_timing_find_mode(XFER_PIO_0 + mode); |
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/* PIO Data Setup */ |
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t0 = DIV_ROUND_UP(cycletime, ideclk_period); |
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t2 = DIV_ROUND_UP(t->active, ideclk_period); |
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t2i = t0 - t2 - 1; |
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t2 -= 1; |
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val32 = readl(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (t2 << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_DATSTB); |
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val32 = readl(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (t2i << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_DATRCVR); |
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if (mate) { |
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u8 mode2 = mate->pio_mode - XFER_PIO_0; |
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if (mode2 < mode) |
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mode = mode2; |
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} |
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/* TASKFILE Setup */ |
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t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period); |
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t2 = DIV_ROUND_UP(t->act8b, ideclk_period); |
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t2i = t0 - t2 - 1; |
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t2 -= 1; |
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val32 = readl(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (t2 << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_REGSTB); |
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val32 = readl(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); |
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val32 |= (t2i << (dev ? 8 : 0)); |
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writel(val32, base + BK3710_REGRCVR); |
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} |
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static void palm_bk3710_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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int is_slave = drive->dn & 1; |
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void __iomem *base = (void __iomem *)hwif->dma_base; |
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const u8 xferspeed = drive->dma_mode; |
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if (xferspeed >= XFER_UDMA_0) { |
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palm_bk3710_setudmamode(base, is_slave, |
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xferspeed - XFER_UDMA_0); |
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} else { |
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palm_bk3710_setdmamode(base, is_slave, |
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drive->id[ATA_ID_EIDE_DMA_MIN], |
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xferspeed); |
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} |
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} |
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static void palm_bk3710_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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unsigned int cycle_time; |
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int is_slave = drive->dn & 1; |
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ide_drive_t *mate; |
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void __iomem *base = (void __iomem *)hwif->dma_base; |
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const u8 pio = drive->pio_mode - XFER_PIO_0; |
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/* |
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* Obtain the drive PIO data for tuning the Palm Chip registers |
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*/ |
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cycle_time = ide_pio_cycle_time(drive, pio); |
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mate = ide_get_pair_dev(drive); |
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palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio); |
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} |
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static void palm_bk3710_chipinit(void __iomem *base) |
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{ |
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/* |
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* REVISIT: the ATA reset signal needs to be managed through a |
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* GPIO, which means it should come from platform_data. Until |
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* we get and use such information, we have to trust that things |
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* have been reset before we get here. |
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*/ |
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/* |
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* Program the IDETIMP Register Value based on the following assumptions |
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* |
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* (ATA_IDETIMP_IDEEN , ENABLE ) | |
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* (ATA_IDETIMP_PREPOST1 , DISABLE) | |
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* (ATA_IDETIMP_PREPOST0 , DISABLE) | |
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* |
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* DM6446 silicon rev 2.1 and earlier have no observed net benefit |
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* from enabling prefetch/postwrite. |
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*/ |
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writew(BIT(15), base + BK3710_IDETIMP); |
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/* |
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* UDMACTL Ultra-ATA DMA Control |
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* (ATA_UDMACTL_UDMAP1 , 0 ) | |
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* (ATA_UDMACTL_UDMAP0 , 0 ) |
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* |
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*/ |
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writew(0, base + BK3710_UDMACTL); |
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/* |
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* MISCCTL Miscellaneous Conrol Register |
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* (ATA_MISCCTL_HWNHLD1P , 1 cycle) |
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* (ATA_MISCCTL_HWNHLD0P , 1 cycle) |
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* (ATA_MISCCTL_TIMORIDE , 1) |
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*/ |
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writel(0x001, base + BK3710_MISCCTL); |
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/* |
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* IORDYTMP IORDY Timer for Primary Register |
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* (ATA_IORDYTMP_IORDYTMP , 0xffff ) |
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*/ |
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writel(0xFFFF, base + BK3710_IORDYTMP); |
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/* |
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* Configure BMISP Register |
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* (ATA_BMISP_DMAEN1 , DISABLE ) | |
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* (ATA_BMISP_DMAEN0 , DISABLE ) | |
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* (ATA_BMISP_IORDYINT , CLEAR) | |
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* (ATA_BMISP_INTRSTAT , CLEAR) | |
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* (ATA_BMISP_DMAERROR , CLEAR) |
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*/ |
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writew(0, base + BK3710_BMISP); |
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palm_bk3710_setpiomode(base, NULL, 0, 600, 0); |
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palm_bk3710_setpiomode(base, NULL, 1, 600, 0); |
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} |
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static u8 palm_bk3710_cable_detect(ide_hwif_t *hwif) |
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{ |
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return ATA_CBL_PATA80; |
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} |
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static int palm_bk3710_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
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{ |
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printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); |
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if (ide_allocate_dma_engine(hwif)) |
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return -1; |
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hwif->dma_base = hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET; |
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return 0; |
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} |
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static const struct ide_port_ops palm_bk3710_ports_ops = { |
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.set_pio_mode = palm_bk3710_set_pio_mode, |
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.set_dma_mode = palm_bk3710_set_dma_mode, |
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.cable_detect = palm_bk3710_cable_detect, |
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}; |
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static struct ide_port_info palm_bk3710_port_info __initdata = { |
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.init_dma = palm_bk3710_init_dma, |
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.port_ops = &palm_bk3710_ports_ops, |
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.dma_ops = &sff_dma_ops, |
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.host_flags = IDE_HFLAG_MMIO, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.chipset = ide_palm3710, |
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}; |
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static int __init palm_bk3710_probe(struct platform_device *pdev) |
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{ |
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struct clk *clk; |
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struct resource *mem, *irq; |
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void __iomem *base; |
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unsigned long rate, mem_size; |
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int i, rc; |
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struct ide_hw hw, *hws[] = { &hw }; |
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clk = clk_get(&pdev->dev, NULL); |
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if (IS_ERR(clk)) |
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return -ENODEV; |
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clk_enable(clk); |
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rate = clk_get_rate(clk); |
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if (!rate) |
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return -EINVAL; |
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/* NOTE: round *down* to meet minimum timings; we count in clocks */ |
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ideclk_period = 1000000000UL / rate; |
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (mem == NULL) { |
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printk(KERN_ERR "failed to get memory region resource\n"); |
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return -ENODEV; |
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} |
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
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if (irq == NULL) { |
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printk(KERN_ERR "failed to get IRQ resource\n"); |
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return -ENODEV; |
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} |
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mem_size = resource_size(mem); |
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if (request_mem_region(mem->start, mem_size, "palm_bk3710") == NULL) { |
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printk(KERN_ERR "failed to request memory region\n"); |
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return -EBUSY; |
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} |
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base = ioremap(mem->start, mem_size); |
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if (!base) { |
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printk(KERN_ERR "failed to map IO memory\n"); |
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release_mem_region(mem->start, mem_size); |
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return -ENOMEM; |
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} |
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/* Configure the Palm Chip controller */ |
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palm_bk3710_chipinit(base); |
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memset(&hw, 0, sizeof(hw)); |
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for (i = 0; i < IDE_NR_PORTS - 2; i++) |
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hw.io_ports_array[i] = (unsigned long) |
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(base + IDE_PALM_ATA_PRI_REG_OFFSET + i); |
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hw.io_ports.ctl_addr = (unsigned long) |
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(base + IDE_PALM_ATA_PRI_CTL_OFFSET); |
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hw.irq = irq->start; |
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hw.dev = &pdev->dev; |
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palm_bk3710_port_info.udma_mask = rate < 100000000 ? ATA_UDMA4 : |
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ATA_UDMA5; |
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/* Register the IDE interface with Linux */ |
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rc = ide_host_add(&palm_bk3710_port_info, hws, 1, NULL); |
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if (rc) |
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goto out; |
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return 0; |
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out: |
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printk(KERN_WARNING "Palm Chip BK3710 IDE Register Fail\n"); |
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return rc; |
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} |
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/* work with hotplug and coldplug */ |
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MODULE_ALIAS("platform:palm_bk3710"); |
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static struct platform_driver platform_bk_driver = { |
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.driver = { |
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.name = "palm_bk3710", |
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}, |
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}; |
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static int __init palm_bk3710_init(void) |
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{ |
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return platform_driver_probe(&platform_bk_driver, palm_bk3710_probe); |
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} |
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module_init(palm_bk3710_init); |
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MODULE_LICENSE("GPL");
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