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350 lines
9.0 KiB
350 lines
9.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 1997-1998 Mark Lord <[email protected]> |
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* Copyright (C) 1998 Eddie C. Dost <[email protected]> |
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* Copyright (C) 1999-2000 Andre Hedrick <[email protected]> |
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* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org> |
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* |
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* Inspired by an earlier effort from David S. Miller <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <linux/interrupt.h> |
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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#include <linux/ide.h> |
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#include <linux/init.h> |
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#include <asm/io.h> |
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#define DRV_NAME "ns87415" |
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#ifdef CONFIG_SUPERIO |
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/* SUPERIO 87560 is a PoS chip that NatSem denies exists. |
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* Unfortunately, it's built-in on all Astro-based PA-RISC workstations |
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* which use the integrated NS87514 cell for CD-ROM support. |
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* i.e we have to support for CD-ROM installs. |
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* See drivers/parisc/superio.c for more gory details. |
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*/ |
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#include <asm/superio.h> |
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#define SUPERIO_IDE_MAX_RETRIES 25 |
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/* Because of a defect in Super I/O, all reads of the PCI DMA status |
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* registers, IDE status register and the IDE select register need to be |
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* retried |
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*/ |
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static u8 superio_ide_inb (unsigned long port) |
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{ |
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u8 tmp; |
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int retries = SUPERIO_IDE_MAX_RETRIES; |
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/* printk(" [ reading port 0x%x with retry ] ", port); */ |
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do { |
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tmp = inb(port); |
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if (tmp == 0) |
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udelay(50); |
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} while (tmp == 0 && retries-- > 0); |
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return tmp; |
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} |
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static u8 superio_read_status(ide_hwif_t *hwif) |
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{ |
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return superio_ide_inb(hwif->io_ports.status_addr); |
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} |
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static u8 superio_dma_sff_read_status(ide_hwif_t *hwif) |
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{ |
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return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS); |
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} |
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static void superio_tf_read(ide_drive_t *drive, struct ide_taskfile *tf, |
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u8 valid) |
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{ |
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struct ide_io_ports *io_ports = &drive->hwif->io_ports; |
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if (valid & IDE_VALID_ERROR) |
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tf->error = inb(io_ports->feature_addr); |
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if (valid & IDE_VALID_NSECT) |
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tf->nsect = inb(io_ports->nsect_addr); |
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if (valid & IDE_VALID_LBAL) |
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tf->lbal = inb(io_ports->lbal_addr); |
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if (valid & IDE_VALID_LBAM) |
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tf->lbam = inb(io_ports->lbam_addr); |
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if (valid & IDE_VALID_LBAH) |
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tf->lbah = inb(io_ports->lbah_addr); |
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if (valid & IDE_VALID_DEVICE) |
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tf->device = superio_ide_inb(io_ports->device_addr); |
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} |
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static void ns87415_dev_select(ide_drive_t *drive); |
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static const struct ide_tp_ops superio_tp_ops = { |
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.exec_command = ide_exec_command, |
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.read_status = superio_read_status, |
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.read_altstatus = ide_read_altstatus, |
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.write_devctl = ide_write_devctl, |
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.dev_select = ns87415_dev_select, |
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.tf_load = ide_tf_load, |
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.tf_read = superio_tf_read, |
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.input_data = ide_input_data, |
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.output_data = ide_output_data, |
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}; |
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static void superio_init_iops(struct hwif_s *hwif) |
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{ |
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struct pci_dev *pdev = to_pci_dev(hwif->dev); |
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u32 dma_stat; |
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u8 port = hwif->channel, tmp; |
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dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa); |
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/* Clear error/interrupt, enable dma */ |
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tmp = superio_ide_inb(dma_stat); |
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outb(tmp | 0x66, dma_stat); |
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} |
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#else |
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#define superio_dma_sff_read_status ide_dma_sff_read_status |
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#endif |
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static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 }; |
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/* |
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* This routine either enables/disables (according to IDE_DFLAG_PRESENT) |
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* the IRQ associated with the port, |
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* and selects either PIO or DMA handshaking for the next I/O operation. |
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*/ |
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static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data; |
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unsigned long flags; |
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local_irq_save(flags); |
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new = *old; |
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/* Adjust IRQ enable bit */ |
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bit = 1 << (8 + hwif->channel); |
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if (drive->dev_flags & IDE_DFLAG_PRESENT) |
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new &= ~bit; |
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else |
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new |= bit; |
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/* Select PIO or DMA, DMA may only be selected for one drive/channel. */ |
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bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1)); |
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other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1)); |
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new = use_dma ? ((new & ~other) | bit) : (new & ~bit); |
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if (new != *old) { |
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unsigned char stat; |
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/* |
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* Don't change DMA engine settings while Write Buffers |
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* are busy. |
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*/ |
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(void) pci_read_config_byte(dev, 0x43, &stat); |
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while (stat & 0x03) { |
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udelay(1); |
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(void) pci_read_config_byte(dev, 0x43, &stat); |
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} |
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*old = new; |
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(void) pci_write_config_dword(dev, 0x40, new); |
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/* |
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* And let things settle... |
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*/ |
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udelay(10); |
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} |
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local_irq_restore(flags); |
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} |
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static void ns87415_dev_select(ide_drive_t *drive) |
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{ |
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ns87415_prepare_drive(drive, |
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!!(drive->dev_flags & IDE_DFLAG_USING_DMA)); |
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outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr); |
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} |
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static void ns87415_dma_start(ide_drive_t *drive) |
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{ |
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ns87415_prepare_drive(drive, 1); |
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ide_dma_start(drive); |
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} |
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static int ns87415_dma_end(ide_drive_t *drive) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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u8 dma_stat = 0, dma_cmd = 0; |
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dma_stat = hwif->dma_ops->dma_sff_read_status(hwif); |
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/* get DMA command mode */ |
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dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
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/* stop DMA */ |
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outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD); |
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/* from ERRATA: clear the INTR & ERROR bits */ |
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dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD); |
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outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD); |
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ns87415_prepare_drive(drive, 0); |
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/* verify good DMA status */ |
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return (dma_stat & 7) != 4; |
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} |
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static void init_hwif_ns87415 (ide_hwif_t *hwif) |
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{ |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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unsigned int ctrl, using_inta; |
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u8 progif; |
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#ifdef __sparc_v9__ |
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int timeout; |
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u8 stat; |
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#endif |
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/* |
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* We cannot probe for IRQ: both ports share common IRQ on INTA. |
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* Also, leave IRQ masked during drive probing, to prevent infinite |
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* interrupts from a potentially floating INTA.. |
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* |
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* IRQs get unmasked in dev_select() when drive is first used. |
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*/ |
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(void) pci_read_config_dword(dev, 0x40, &ctrl); |
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(void) pci_read_config_byte(dev, 0x09, &progif); |
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/* is irq in "native" mode? */ |
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using_inta = progif & (1 << (hwif->channel << 1)); |
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if (!using_inta) |
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using_inta = ctrl & (1 << (4 + hwif->channel)); |
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if (hwif->mate) { |
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hwif->select_data = hwif->mate->select_data; |
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} else { |
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hwif->select_data = (unsigned long) |
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&ns87415_control[ns87415_count++]; |
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ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */ |
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if (using_inta) |
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ctrl &= ~(1 << 6); /* unmask INTA */ |
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*((unsigned int *)hwif->select_data) = ctrl; |
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(void) pci_write_config_dword(dev, 0x40, ctrl); |
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/* |
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* Set prefetch size to 512 bytes for both ports, |
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* but don't turn on/off prefetching here. |
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*/ |
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pci_write_config_byte(dev, 0x55, 0xee); |
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#ifdef __sparc_v9__ |
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/* |
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* XXX: Reset the device, if we don't it will not respond to |
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* dev_select() properly during first ide_probe_port(). |
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*/ |
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timeout = 10000; |
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outb(12, hwif->io_ports.ctl_addr); |
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udelay(10); |
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outb(8, hwif->io_ports.ctl_addr); |
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do { |
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udelay(50); |
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stat = hwif->tp_ops->read_status(hwif); |
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if (stat == 0xff) |
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break; |
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} while ((stat & ATA_BUSY) && --timeout); |
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#endif |
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} |
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if (!using_inta) |
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hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel); |
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if (!hwif->dma_base) |
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return; |
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outb(0x60, hwif->dma_base + ATA_DMA_STATUS); |
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} |
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static const struct ide_tp_ops ns87415_tp_ops = { |
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.exec_command = ide_exec_command, |
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.read_status = ide_read_status, |
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.read_altstatus = ide_read_altstatus, |
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.write_devctl = ide_write_devctl, |
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.dev_select = ns87415_dev_select, |
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.tf_load = ide_tf_load, |
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.tf_read = ide_tf_read, |
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.input_data = ide_input_data, |
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.output_data = ide_output_data, |
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}; |
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static const struct ide_dma_ops ns87415_dma_ops = { |
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.dma_host_set = ide_dma_host_set, |
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.dma_setup = ide_dma_setup, |
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.dma_start = ns87415_dma_start, |
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.dma_end = ns87415_dma_end, |
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.dma_test_irq = ide_dma_test_irq, |
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.dma_lost_irq = ide_dma_lost_irq, |
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.dma_timer_expiry = ide_dma_sff_timer_expiry, |
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.dma_sff_read_status = superio_dma_sff_read_status, |
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}; |
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static const struct ide_port_info ns87415_chipset = { |
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.name = DRV_NAME, |
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.init_hwif = init_hwif_ns87415, |
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.tp_ops = &ns87415_tp_ops, |
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.dma_ops = &ns87415_dma_ops, |
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.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | |
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IDE_HFLAG_NO_ATAPI_DMA, |
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}; |
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static int ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
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{ |
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struct ide_port_info d = ns87415_chipset; |
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#ifdef CONFIG_SUPERIO |
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if (PCI_SLOT(dev->devfn) == 0xE) { |
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/* Built-in - assume it's under superio. */ |
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d.init_iops = superio_init_iops; |
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d.tp_ops = &superio_tp_ops; |
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} |
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#endif |
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return ide_pci_init_one(dev, &d, NULL); |
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} |
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static const struct pci_device_id ns87415_pci_tbl[] = { |
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{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 }, |
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{ 0, }, |
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}; |
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MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl); |
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static struct pci_driver ns87415_pci_driver = { |
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.name = "NS87415_IDE", |
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.id_table = ns87415_pci_tbl, |
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.probe = ns87415_init_one, |
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.remove = ide_pci_remove, |
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.suspend = ide_pci_suspend, |
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.resume = ide_pci_resume, |
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}; |
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static int __init ns87415_ide_init(void) |
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{ |
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return ide_pci_register_driver(&ns87415_pci_driver); |
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} |
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static void __exit ns87415_ide_exit(void) |
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{ |
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pci_unregister_driver(&ns87415_pci_driver); |
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} |
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module_init(ns87415_ide_init); |
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module_exit(ns87415_ide_exit); |
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MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick"); |
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MODULE_DESCRIPTION("PCI driver module for NS87415 IDE"); |
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MODULE_LICENSE("GPL");
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