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740 lines
20 KiB
740 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Xilinx gpio driver for xps/axi_gpio IP. |
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* |
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* Copyright 2008 - 2013 Xilinx, Inc. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/errno.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/of_platform.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/slab.h> |
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/* Register Offset Definitions */ |
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#define XGPIO_DATA_OFFSET (0x0) /* Data register */ |
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#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ |
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#define XGPIO_CHANNEL_OFFSET 0x8 |
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#define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ |
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#define XGPIO_GIER_IE BIT(31) |
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#define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ |
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#define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ |
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/* Read/Write access to the GPIO registers */ |
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#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) |
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# define xgpio_readreg(offset) readl(offset) |
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# define xgpio_writereg(offset, val) writel(val, offset) |
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#else |
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# define xgpio_readreg(offset) __raw_readl(offset) |
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# define xgpio_writereg(offset, val) __raw_writel(val, offset) |
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#endif |
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/** |
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* struct xgpio_instance - Stores information about GPIO device |
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* @gc: GPIO chip |
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* @regs: register block |
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* @gpio_width: GPIO width for every channel |
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* @gpio_state: GPIO write state shadow register |
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* @gpio_last_irq_read: GPIO read state register from last interrupt |
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* @gpio_dir: GPIO direction shadow register |
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* @gpio_lock: Lock used for synchronization |
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* @irq: IRQ used by GPIO device |
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* @irqchip: IRQ chip |
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* @irq_enable: GPIO IRQ enable/disable bitfield |
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* @irq_rising_edge: GPIO IRQ rising edge enable/disable bitfield |
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* @irq_falling_edge: GPIO IRQ falling edge enable/disable bitfield |
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* @clk: clock resource for this driver |
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*/ |
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struct xgpio_instance { |
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struct gpio_chip gc; |
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void __iomem *regs; |
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unsigned int gpio_width[2]; |
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u32 gpio_state[2]; |
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u32 gpio_last_irq_read[2]; |
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u32 gpio_dir[2]; |
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spinlock_t gpio_lock; /* For serializing operations */ |
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int irq; |
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struct irq_chip irqchip; |
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u32 irq_enable[2]; |
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u32 irq_rising_edge[2]; |
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u32 irq_falling_edge[2]; |
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struct clk *clk; |
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}; |
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static inline int xgpio_index(struct xgpio_instance *chip, int gpio) |
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{ |
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if (gpio >= chip->gpio_width[0]) |
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return 1; |
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return 0; |
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} |
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static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio) |
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{ |
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if (xgpio_index(chip, gpio)) |
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return XGPIO_CHANNEL_OFFSET; |
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return 0; |
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} |
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static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) |
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{ |
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if (xgpio_index(chip, gpio)) |
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return gpio - chip->gpio_width[0]; |
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return gpio; |
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} |
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/** |
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* xgpio_get - Read the specified signal of the GPIO device. |
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* @gc: Pointer to gpio_chip device structure. |
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* @gpio: GPIO signal number. |
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* |
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* This function reads the specified signal of the GPIO device. |
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* |
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* Return: |
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* 0 if direction of GPIO signals is set as input otherwise it |
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* returns negative error value. |
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*/ |
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static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) |
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{ |
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struct xgpio_instance *chip = gpiochip_get_data(gc); |
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u32 val; |
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val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + |
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xgpio_regoffset(chip, gpio)); |
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return !!(val & BIT(xgpio_offset(chip, gpio))); |
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} |
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/** |
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* xgpio_set - Write the specified signal of the GPIO device. |
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* @gc: Pointer to gpio_chip device structure. |
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* @gpio: GPIO signal number. |
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* @val: Value to be written to specified signal. |
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* |
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* This function writes the specified value in to the specified signal of the |
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* GPIO device. |
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*/ |
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static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
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{ |
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unsigned long flags; |
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struct xgpio_instance *chip = gpiochip_get_data(gc); |
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int index = xgpio_index(chip, gpio); |
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int offset = xgpio_offset(chip, gpio); |
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spin_lock_irqsave(&chip->gpio_lock, flags); |
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/* Write to GPIO signal and set its direction to output */ |
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if (val) |
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chip->gpio_state[index] |= BIT(offset); |
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else |
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chip->gpio_state[index] &= ~BIT(offset); |
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + |
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xgpio_regoffset(chip, gpio), chip->gpio_state[index]); |
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spin_unlock_irqrestore(&chip->gpio_lock, flags); |
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} |
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/** |
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* xgpio_set_multiple - Write the specified signals of the GPIO device. |
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* @gc: Pointer to gpio_chip device structure. |
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* @mask: Mask of the GPIOS to modify. |
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* @bits: Value to be wrote on each GPIO |
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* |
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* This function writes the specified values into the specified signals of the |
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* GPIO devices. |
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*/ |
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static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, |
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unsigned long *bits) |
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{ |
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unsigned long flags; |
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struct xgpio_instance *chip = gpiochip_get_data(gc); |
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int index = xgpio_index(chip, 0); |
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int offset, i; |
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spin_lock_irqsave(&chip->gpio_lock, flags); |
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/* Write to GPIO signals */ |
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for (i = 0; i < gc->ngpio; i++) { |
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if (*mask == 0) |
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break; |
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/* Once finished with an index write it out to the register */ |
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if (index != xgpio_index(chip, i)) { |
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + |
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index * XGPIO_CHANNEL_OFFSET, |
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chip->gpio_state[index]); |
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spin_unlock_irqrestore(&chip->gpio_lock, flags); |
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index = xgpio_index(chip, i); |
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spin_lock_irqsave(&chip->gpio_lock, flags); |
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} |
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if (__test_and_clear_bit(i, mask)) { |
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offset = xgpio_offset(chip, i); |
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if (test_bit(i, bits)) |
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chip->gpio_state[index] |= BIT(offset); |
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else |
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chip->gpio_state[index] &= ~BIT(offset); |
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} |
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} |
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + |
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index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); |
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spin_unlock_irqrestore(&chip->gpio_lock, flags); |
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} |
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/** |
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* xgpio_dir_in - Set the direction of the specified GPIO signal as input. |
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* @gc: Pointer to gpio_chip device structure. |
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* @gpio: GPIO signal number. |
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* |
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* Return: |
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* 0 - if direction of GPIO signals is set as input |
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* otherwise it returns negative error value. |
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*/ |
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static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
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{ |
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unsigned long flags; |
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struct xgpio_instance *chip = gpiochip_get_data(gc); |
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int index = xgpio_index(chip, gpio); |
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int offset = xgpio_offset(chip, gpio); |
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spin_lock_irqsave(&chip->gpio_lock, flags); |
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/* Set the GPIO bit in shadow register and set direction as input */ |
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chip->gpio_dir[index] |= BIT(offset); |
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xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + |
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xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); |
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spin_unlock_irqrestore(&chip->gpio_lock, flags); |
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return 0; |
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} |
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/** |
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* xgpio_dir_out - Set the direction of the specified GPIO signal as output. |
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* @gc: Pointer to gpio_chip device structure. |
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* @gpio: GPIO signal number. |
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* @val: Value to be written to specified signal. |
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* |
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* This function sets the direction of specified GPIO signal as output. |
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* |
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* Return: |
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* If all GPIO signals of GPIO chip is configured as input then it returns |
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* error otherwise it returns 0. |
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*/ |
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static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
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{ |
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unsigned long flags; |
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struct xgpio_instance *chip = gpiochip_get_data(gc); |
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int index = xgpio_index(chip, gpio); |
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int offset = xgpio_offset(chip, gpio); |
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spin_lock_irqsave(&chip->gpio_lock, flags); |
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/* Write state of GPIO signal */ |
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if (val) |
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chip->gpio_state[index] |= BIT(offset); |
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else |
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chip->gpio_state[index] &= ~BIT(offset); |
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + |
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xgpio_regoffset(chip, gpio), chip->gpio_state[index]); |
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/* Clear the GPIO bit in shadow register and set direction as output */ |
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chip->gpio_dir[index] &= ~BIT(offset); |
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xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + |
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xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); |
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spin_unlock_irqrestore(&chip->gpio_lock, flags); |
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return 0; |
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} |
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/** |
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* xgpio_save_regs - Set initial values of GPIO pins |
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* @chip: Pointer to GPIO instance |
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*/ |
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static void xgpio_save_regs(struct xgpio_instance *chip) |
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{ |
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]); |
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xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]); |
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if (!chip->gpio_width[1]) |
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return; |
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xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET, |
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chip->gpio_state[1]); |
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xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET, |
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chip->gpio_dir[1]); |
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} |
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static int xgpio_request(struct gpio_chip *chip, unsigned int offset) |
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{ |
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int ret; |
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ret = pm_runtime_get_sync(chip->parent); |
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/* |
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* If the device is already active pm_runtime_get() will return 1 on |
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* success, but gpio_request still needs to return 0. |
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*/ |
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return ret < 0 ? ret : 0; |
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} |
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static void xgpio_free(struct gpio_chip *chip, unsigned int offset) |
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{ |
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pm_runtime_put(chip->parent); |
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} |
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static int __maybe_unused xgpio_suspend(struct device *dev) |
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{ |
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struct xgpio_instance *gpio = dev_get_drvdata(dev); |
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struct irq_data *data = irq_get_irq_data(gpio->irq); |
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if (!data) { |
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dev_err(dev, "irq_get_irq_data() failed\n"); |
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return -EINVAL; |
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} |
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if (!irqd_is_wakeup_set(data)) |
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return pm_runtime_force_suspend(dev); |
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return 0; |
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} |
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/** |
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* xgpio_remove - Remove method for the GPIO device. |
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* @pdev: pointer to the platform device |
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* |
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* This function remove gpiochips and frees all the allocated resources. |
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* |
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* Return: 0 always |
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*/ |
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static int xgpio_remove(struct platform_device *pdev) |
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{ |
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struct xgpio_instance *gpio = platform_get_drvdata(pdev); |
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pm_runtime_get_sync(&pdev->dev); |
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pm_runtime_put_noidle(&pdev->dev); |
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pm_runtime_disable(&pdev->dev); |
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clk_disable_unprepare(gpio->clk); |
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return 0; |
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} |
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/** |
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* xgpio_irq_ack - Acknowledge a child GPIO interrupt. |
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* @irq_data: per IRQ and chip data passed down to chip functions |
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* This currently does nothing, but irq_ack is unconditionally called by |
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* handle_edge_irq and therefore must be defined. |
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*/ |
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static void xgpio_irq_ack(struct irq_data *irq_data) |
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{ |
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} |
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static int __maybe_unused xgpio_resume(struct device *dev) |
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{ |
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struct xgpio_instance *gpio = dev_get_drvdata(dev); |
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struct irq_data *data = irq_get_irq_data(gpio->irq); |
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if (!data) { |
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dev_err(dev, "irq_get_irq_data() failed\n"); |
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return -EINVAL; |
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} |
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if (!irqd_is_wakeup_set(data)) |
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return pm_runtime_force_resume(dev); |
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return 0; |
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} |
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static int __maybe_unused xgpio_runtime_suspend(struct device *dev) |
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{ |
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struct platform_device *pdev = to_platform_device(dev); |
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struct xgpio_instance *gpio = platform_get_drvdata(pdev); |
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clk_disable(gpio->clk); |
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return 0; |
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} |
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static int __maybe_unused xgpio_runtime_resume(struct device *dev) |
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{ |
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struct platform_device *pdev = to_platform_device(dev); |
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struct xgpio_instance *gpio = platform_get_drvdata(pdev); |
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return clk_enable(gpio->clk); |
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} |
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static const struct dev_pm_ops xgpio_dev_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) |
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SET_RUNTIME_PM_OPS(xgpio_runtime_suspend, |
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xgpio_runtime_resume, NULL) |
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}; |
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/** |
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* xgpio_irq_mask - Write the specified signal of the GPIO device. |
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* @irq_data: per IRQ and chip data passed down to chip functions |
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*/ |
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static void xgpio_irq_mask(struct irq_data *irq_data) |
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{ |
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unsigned long flags; |
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); |
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int irq_offset = irqd_to_hwirq(irq_data); |
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int index = xgpio_index(chip, irq_offset); |
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int offset = xgpio_offset(chip, irq_offset); |
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spin_lock_irqsave(&chip->gpio_lock, flags); |
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chip->irq_enable[index] &= ~BIT(offset); |
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if (!chip->irq_enable[index]) { |
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/* Disable per channel interrupt */ |
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u32 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); |
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temp &= ~BIT(index); |
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xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); |
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} |
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spin_unlock_irqrestore(&chip->gpio_lock, flags); |
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} |
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/** |
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* xgpio_irq_unmask - Write the specified signal of the GPIO device. |
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* @irq_data: per IRQ and chip data passed down to chip functions |
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*/ |
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static void xgpio_irq_unmask(struct irq_data *irq_data) |
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{ |
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unsigned long flags; |
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); |
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int irq_offset = irqd_to_hwirq(irq_data); |
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int index = xgpio_index(chip, irq_offset); |
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int offset = xgpio_offset(chip, irq_offset); |
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u32 old_enable = chip->irq_enable[index]; |
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spin_lock_irqsave(&chip->gpio_lock, flags); |
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chip->irq_enable[index] |= BIT(offset); |
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if (!old_enable) { |
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/* Clear any existing per-channel interrupts */ |
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u32 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET) & |
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BIT(index); |
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if (val) |
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xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); |
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/* Update GPIO IRQ read data before enabling interrupt*/ |
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val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + |
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index * XGPIO_CHANNEL_OFFSET); |
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chip->gpio_last_irq_read[index] = val; |
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/* Enable per channel interrupt */ |
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val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); |
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val |= BIT(index); |
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xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); |
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} |
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spin_unlock_irqrestore(&chip->gpio_lock, flags); |
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} |
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/** |
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* xgpio_set_irq_type - Write the specified signal of the GPIO device. |
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* @irq_data: Per IRQ and chip data passed down to chip functions |
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* @type: Interrupt type that is to be set for the gpio pin |
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* |
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* Return: |
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* 0 if interrupt type is supported otherwise -EINVAL |
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*/ |
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static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) |
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{ |
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struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); |
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int irq_offset = irqd_to_hwirq(irq_data); |
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int index = xgpio_index(chip, irq_offset); |
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int offset = xgpio_offset(chip, irq_offset); |
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/* |
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* The Xilinx GPIO hardware provides a single interrupt status |
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* indication for any state change in a given GPIO channel (bank). |
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* Therefore, only rising edge or falling edge triggers are |
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* supported. |
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*/ |
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switch (type & IRQ_TYPE_SENSE_MASK) { |
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case IRQ_TYPE_EDGE_BOTH: |
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chip->irq_rising_edge[index] |= BIT(offset); |
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chip->irq_falling_edge[index] |= BIT(offset); |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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chip->irq_rising_edge[index] |= BIT(offset); |
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chip->irq_falling_edge[index] &= ~BIT(offset); |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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chip->irq_rising_edge[index] &= ~BIT(offset); |
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chip->irq_falling_edge[index] |= BIT(offset); |
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break; |
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default: |
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return -EINVAL; |
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} |
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irq_set_handler_locked(irq_data, handle_edge_irq); |
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return 0; |
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} |
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/** |
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* xgpio_irqhandler - Gpio interrupt service routine |
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* @desc: Pointer to interrupt description |
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*/ |
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static void xgpio_irqhandler(struct irq_desc *desc) |
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{ |
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struct xgpio_instance *chip = irq_desc_get_handler_data(desc); |
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struct irq_chip *irqchip = irq_desc_get_chip(desc); |
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u32 num_channels = chip->gpio_width[1] ? 2 : 1; |
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u32 offset = 0, index; |
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u32 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
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xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); |
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chained_irq_enter(irqchip, desc); |
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for (index = 0; index < num_channels; index++) { |
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if ((status & BIT(index))) { |
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unsigned long rising_events, falling_events, all_events; |
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unsigned long flags; |
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u32 data, bit; |
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unsigned int irq; |
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spin_lock_irqsave(&chip->gpio_lock, flags); |
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data = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + |
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index * XGPIO_CHANNEL_OFFSET); |
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rising_events = data & |
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~chip->gpio_last_irq_read[index] & |
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chip->irq_enable[index] & |
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chip->irq_rising_edge[index]; |
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falling_events = ~data & |
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chip->gpio_last_irq_read[index] & |
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chip->irq_enable[index] & |
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chip->irq_falling_edge[index]; |
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dev_dbg(chip->gc.parent, |
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"IRQ chan %u rising 0x%lx falling 0x%lx\n", |
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index, rising_events, falling_events); |
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all_events = rising_events | falling_events; |
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chip->gpio_last_irq_read[index] = data; |
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spin_unlock_irqrestore(&chip->gpio_lock, flags); |
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for_each_set_bit(bit, &all_events, 32) { |
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irq = irq_find_mapping(chip->gc.irq.domain, |
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offset + bit); |
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generic_handle_irq(irq); |
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} |
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} |
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offset += chip->gpio_width[index]; |
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} |
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chained_irq_exit(irqchip, desc); |
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} |
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|
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/** |
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* xgpio_of_probe - Probe method for the GPIO device. |
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* @pdev: pointer to the platform device |
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* |
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* Return: |
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* It returns 0, if the driver is bound to the GPIO device, or |
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* a negative value if there is an error. |
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*/ |
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static int xgpio_probe(struct platform_device *pdev) |
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{ |
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struct xgpio_instance *chip; |
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int status = 0; |
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struct device_node *np = pdev->dev.of_node; |
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u32 is_dual = 0; |
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u32 cells = 2; |
|
struct gpio_irq_chip *girq; |
|
u32 temp; |
|
|
|
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
|
if (!chip) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, chip); |
|
|
|
/* Update GPIO state shadow register with default value */ |
|
if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0])) |
|
chip->gpio_state[0] = 0x0; |
|
|
|
/* Update GPIO direction shadow register with default value */ |
|
if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0])) |
|
chip->gpio_dir[0] = 0xFFFFFFFF; |
|
|
|
/* Update cells with gpio-cells value */ |
|
if (of_property_read_u32(np, "#gpio-cells", &cells)) |
|
dev_dbg(&pdev->dev, "Missing gpio-cells property\n"); |
|
|
|
if (cells != 2) { |
|
dev_err(&pdev->dev, "#gpio-cells mismatch\n"); |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* Check device node and parent device node for device width |
|
* and assume default width of 32 |
|
*/ |
|
if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0])) |
|
chip->gpio_width[0] = 32; |
|
|
|
if (chip->gpio_width[0] > 32) |
|
return -EINVAL; |
|
|
|
spin_lock_init(&chip->gpio_lock); |
|
|
|
if (of_property_read_u32(np, "xlnx,is-dual", &is_dual)) |
|
is_dual = 0; |
|
|
|
if (is_dual) { |
|
/* Update GPIO state shadow register with default value */ |
|
if (of_property_read_u32(np, "xlnx,dout-default-2", |
|
&chip->gpio_state[1])) |
|
chip->gpio_state[1] = 0x0; |
|
|
|
/* Update GPIO direction shadow register with default value */ |
|
if (of_property_read_u32(np, "xlnx,tri-default-2", |
|
&chip->gpio_dir[1])) |
|
chip->gpio_dir[1] = 0xFFFFFFFF; |
|
|
|
/* |
|
* Check device node and parent device node for device width |
|
* and assume default width of 32 |
|
*/ |
|
if (of_property_read_u32(np, "xlnx,gpio2-width", |
|
&chip->gpio_width[1])) |
|
chip->gpio_width[1] = 32; |
|
|
|
if (chip->gpio_width[1] > 32) |
|
return -EINVAL; |
|
} |
|
|
|
chip->gc.base = -1; |
|
chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1]; |
|
chip->gc.parent = &pdev->dev; |
|
chip->gc.direction_input = xgpio_dir_in; |
|
chip->gc.direction_output = xgpio_dir_out; |
|
chip->gc.of_gpio_n_cells = cells; |
|
chip->gc.get = xgpio_get; |
|
chip->gc.set = xgpio_set; |
|
chip->gc.request = xgpio_request; |
|
chip->gc.free = xgpio_free; |
|
chip->gc.set_multiple = xgpio_set_multiple; |
|
|
|
chip->gc.label = dev_name(&pdev->dev); |
|
|
|
chip->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(chip->regs)) { |
|
dev_err(&pdev->dev, "failed to ioremap memory resource\n"); |
|
return PTR_ERR(chip->regs); |
|
} |
|
|
|
chip->clk = devm_clk_get_optional(&pdev->dev, NULL); |
|
if (IS_ERR(chip->clk)) |
|
return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n"); |
|
|
|
status = clk_prepare_enable(chip->clk); |
|
if (status < 0) { |
|
dev_err(&pdev->dev, "Failed to prepare clk\n"); |
|
return status; |
|
} |
|
pm_runtime_get_noresume(&pdev->dev); |
|
pm_runtime_set_active(&pdev->dev); |
|
pm_runtime_enable(&pdev->dev); |
|
|
|
xgpio_save_regs(chip); |
|
|
|
chip->irq = platform_get_irq_optional(pdev, 0); |
|
if (chip->irq <= 0) |
|
goto skip_irq; |
|
|
|
chip->irqchip.name = "gpio-xilinx"; |
|
chip->irqchip.irq_ack = xgpio_irq_ack; |
|
chip->irqchip.irq_mask = xgpio_irq_mask; |
|
chip->irqchip.irq_unmask = xgpio_irq_unmask; |
|
chip->irqchip.irq_set_type = xgpio_set_irq_type; |
|
|
|
/* Disable per-channel interrupts */ |
|
xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); |
|
/* Clear any existing per-channel interrupts */ |
|
temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
|
xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); |
|
/* Enable global interrupts */ |
|
xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); |
|
|
|
girq = &chip->gc.irq; |
|
girq->chip = &chip->irqchip; |
|
girq->parent_handler = xgpio_irqhandler; |
|
girq->num_parents = 1; |
|
girq->parents = devm_kcalloc(&pdev->dev, 1, |
|
sizeof(*girq->parents), |
|
GFP_KERNEL); |
|
if (!girq->parents) { |
|
status = -ENOMEM; |
|
goto err_pm_put; |
|
} |
|
girq->parents[0] = chip->irq; |
|
girq->default_type = IRQ_TYPE_NONE; |
|
girq->handler = handle_bad_irq; |
|
|
|
skip_irq: |
|
status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); |
|
if (status) { |
|
dev_err(&pdev->dev, "failed to add GPIO chip\n"); |
|
goto err_pm_put; |
|
} |
|
|
|
pm_runtime_put(&pdev->dev); |
|
return 0; |
|
|
|
err_pm_put: |
|
pm_runtime_disable(&pdev->dev); |
|
pm_runtime_put_noidle(&pdev->dev); |
|
clk_disable_unprepare(chip->clk); |
|
return status; |
|
} |
|
|
|
static const struct of_device_id xgpio_of_match[] = { |
|
{ .compatible = "xlnx,xps-gpio-1.00.a", }, |
|
{ /* end of list */ }, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, xgpio_of_match); |
|
|
|
static struct platform_driver xgpio_plat_driver = { |
|
.probe = xgpio_probe, |
|
.remove = xgpio_remove, |
|
.driver = { |
|
.name = "gpio-xilinx", |
|
.of_match_table = xgpio_of_match, |
|
.pm = &xgpio_dev_pm_ops, |
|
}, |
|
}; |
|
|
|
static int __init xgpio_init(void) |
|
{ |
|
return platform_driver_register(&xgpio_plat_driver); |
|
} |
|
|
|
subsys_initcall(xgpio_init); |
|
|
|
static void __exit xgpio_exit(void) |
|
{ |
|
platform_driver_unregister(&xgpio_plat_driver); |
|
} |
|
module_exit(xgpio_exit); |
|
|
|
MODULE_AUTHOR("Xilinx, Inc."); |
|
MODULE_DESCRIPTION("Xilinx GPIO driver"); |
|
MODULE_LICENSE("GPL");
|
|
|